TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 219

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

16.5 I2C Bus Control
SCL pin
SDA pin
16.5.7 Start/stop condition generation
16.5.8 Interrupt service request and cancel
" Table 16-2 TRX changing conditions in each mode " shows TRX changing conditions in each mode and TRX
value after changing
recognized. They are handled as data just after generating a start condition. The TRX is not changed by a hard-
ware.
output on a bus after generating a start condition by writing “1” to the MST, TRX, BB and PIN. It is necessary
to set ACK to “1” beforehand.
PIN, and “0” to the BB. Do not modify the contents of MST, TRX, BB and PIN until a stop condition is gener-
ated on a bus.
a stop condition is generated after releasing the SCL line.
when a start condition on a bus is detected (Bus Busy State) and is cleared to “0” when a stop condition is
detected (Bus Free State).
and the ACK is complete, a serial bus interface interrupt request (INTSBI) is generated.
Figure 16-5 Start Condition Generation and Slave Address Generation
When a stop condition on the bus or an arbitration lost is detected, the TRX is cleared to “0” by the hardware.
When a serial bus interface circuit operates in the free data format, a slave address and a direction bit are not
When the BB (Bit5 in SBISRB) is “0”, a slave address and a direction bit which are set to the SBIDBR are
When the BB is “1”, sequence of generating a stop condition is started by writing “1” to the MST, TRX and
When a stop condition is generated and the SCL line on a bus is pulled-down to low level by another device,
The bus condition can be indicated by reading the contents of the BB (Bit5 in SBISRB). The BB is set to “1”
When a serial bus interface circuit is in the master mode and transferring a number of clocks set by the BC
Table 16-2 TRX changing conditions in each mode
Start condition
Master
Mode
Slave
Mode
Mode
Figure 16-6 Stop Condition Generation
SCL pin
SDA pin
A6
Direction Bit
1
"0"
"1"
"0"
"1"
A5
2
the same value set to I2CAR
A4
A received slave address is
Slave address and the direction bit
3
ACK signal is returned
Page 202
Conditions
A3
4
Stop condition
A2
5
A1
6
TRX after Changing
A0
"0"
"1"
"1"
"0"
7
R/W
8
Acknowledge signal
TMP86PM49UG
9