TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 62

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TMP86xy49UG/F/NG

Manufacturer Part Number
TMP86xy49UG/F/NG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP86xy49UG/F/NG

Package
LQFP64/QFP64/SDIP64
Rom Types (m=mask,p=otp,f=flash)
M/P/F
Rom Size
16/32/60
Ram Size
512/1K/2K
Driver Led
13
Driver Lcd
-
Spi/sio Channels
2
Uart/sio Channels
2
I2c/sio Channels
1
High-speed Serial Output
-
Adc 8-bit Channels
-
Adc 10-bit Channels
16
Da Converter Channels
-
Timer Counter 18-bit Channel
-
Timer Counter 16-bit Channel
2
Timer Counter 8-bit Channel
4
Motor Channels
-
Watchdog Timer
Y
Dual Clock
Y
Clock Gear
-
Number Of I/o Ports
56
Power Supply (v)
4.5 to 5.5
4. Special Function Register (SFR)
4.1 SFR
formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address
0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH.
TMP86PM49UG.
The TMP86PM49UG adopts the memory mapped I/O system, and all peripheral control and data transfers are per-
This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for
Address
000CH
000DH
001CH
001DH
0000H
0001H
0002H
0003H
0004H
0005H
0006H
0007H
0008H
0009H
000AH
000BH
000EH
000FH
0010H
0012H
0013H
0014H
0015H
0016H
0017H
0018H
0019H
001AH
001BH
001EH
001FH
0020H
0021H
0022H
0023H
0024H
0025H
0011H
SIO1RDB
ADCDR2
ADCDR1
SIO1SR
P0PRD
P2PRD
P3PRD
P4PRD
P5PRD
Read
Page 45
P0OUTCR
P4OUTCR
TC1DRAH
TC1DRBH
TC1DRAL
TC1DRBL
PWREG3
PWREG4
PWREG5
PWREG6
ADCCR1
ADCCR2
TC2DRH
TTREG3
TTREG4
TTREG5
TTREG6
TC2DRL
SIO1CR
TC2CR
P0DR
P1DR
P2DR
P3DR
P4DR
P5DR
P6DR
P7DR
P1CR
SIO1TDB
Write
-
-
-
-
-
-
-
-
TMP86PM49UG

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