MT54V1MH18E Micron Semiconductor Products, Inc., MT54V1MH18E Datasheet
MT54V1MH18E
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MT54V1MH18E Summary of contents
Page 1
... Operating Temperature Range Commercial (0°C £ T £ +70°C) A NOTE Part Marking Guide for the FBGA devices can be found on Micron’s Web site—http://www.micron.com/numberguide. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V MT54V1MH18E SRAM MT54V512H36E Table 1: PART NUMBER MT54V1MH18EF-xx MT54V512H36EF-xx General Description ...
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... V , HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V READ cycles are pipelined. The request is initiated by asserting R# LOW at K rising edge. Data is delivered after the next rising edge of K, using C and C# as the output timing references, or using K and and C# are tied HIGH ...
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... V , HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2. strontly recommended that the clocks operate for a number of cycles prior to initiating commands to the SRAM. This delay permits transmission line charging effects to be overcome and allows the clock timing to be nearer to its steady-state value ...
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... Figure 2 illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for detailed information. 2. For 1 Meg 18. For 512K 36. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 Figure 2: Functional Block Diagram 1 Meg x 18; 512K ...
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... For high frequency applications (200 MHz and faster) the CQ and CQ# clocks (for data capture) are recommended over the C and C# clocks (for data alignment). The C and C# clocks are optional use inputs. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V Figure 3: Application Example R = 250Ω SRAM 1 ...
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... NC NC Q14 L NC Q15 D15 D16 N NC D17 Q16 Q17 R TDO TCK NOTE: 1. Expansion address: 3A for 36Mb 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/ BW1 ...
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... Q35 D35 Q26 R TDO TCK NOTE: 1. BW2# controls writes to D18:D26 2. BW1# controls writes to D9:D17 3. Expansion address: 9A for 36Mb 4. BW3# controls writes to D27:D35 5. BW0# controls writes to D0:D8 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/ BW2 BW3 ...
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... No Connect: These balls are internally connected to the die, but have no function and may be left not connected to the board to minimize ball count. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512K HSTL, QDRb4 SRAM DD DESCRIPTION if the JTAG function is not used in ...
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... State transitions (R# = LOW (W# = LOW). 3. Read and write state machines can be simultaneously active. Read and write cannot be simultaneously initiated; read takes precendence. 4. State machine, control timing sequence is controlled by K. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V Figure 4: Bus Cycle State Diagram RD always INCREMENT READ READ DOUBLE ...
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... The x36 device operation is similar except for the addition of BW2# (controls D18:D26) and BW3# (controls D27:D35). 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2. L® ...
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... Notes appear following parameter tables on page 14; 0°C £ T DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 1) Voltage 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to ..... -0.5V to +3.4V SS the device. This is a stress rating only, and functional ...
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... Clock Capacitance Table 11: Thermal Resistance Note 13; notes appear following parameter tables on page 14 DESCRIPTION Junction to Ambient (Airflow of 1m/s) Junction to Case (Top) Junction to Balls (Bottom) 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 £ +70° SYM TYP ³ Cycle time IL IH TBD ...
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... Control inputs valid to K rising edge Data-in valid rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K# rising edge to data-in hold 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/ SYM MIN MAX MIN MAX t 5.0 6.0 KHKH t 2 ...
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... DD increases with faster cycle times. I with faster cycle times and greater output loading. Typical value is measured at 6ns cycle time. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/ 10. Typical values are measured 1.5V, and temperature = 25° ...
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... Input rise and fall times...................................... 0.7ns Input timing reference levels .............................0.75V Output reference levels...................................V ZQ for 50 W impedance ...........................................250W Output load ..............................................See Figure 5 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512K Output Load Equivalent V Q/2 DD SRAM ZQ Micron Technology, Inc ...
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... Outputs are disabled (High-Z) one clock cycle after a NOP this example, if address A2 = A1, then data Q20 = D10, Q21 = D11, Q22 = D12, Q23 = D13. Write data is forwarded immediately as read results. (This note applies to whole diagram.) 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 Figure 6: READ/WRITE Timing WRITE READ 3 ...
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... The test clock is used only with the TAP controller. All inputs are captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512K HSTL, QDRb4 SRAM DD Figure 7: ...
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... SRAM with mini- mal delay. The bypass register is set LOW (Vss) when the BYPASS instruction is executed. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512K HSTL, QDRb4 SRAM DD Figure 8: TAP Controller Block Diagram ...
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... The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also places the instruction register between the TDI 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512K HSTL, QDRb4 SRAM DD and TDO balls and allows the IDCODE to be shifted out of the device when the TAP controller enters the Shift-DR state ...
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... CS and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V Figure 9: TAP Timing THTL t t THTH ...
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... This table defines DC values for TAP control and data balls only. The DQ SRAM balls used in JTAG operation will have the DC values as defined in Table 7, “DC Electrical Characteristics and Operating Conditions,” on page 11. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V TAP AC Output Load Equivalent to 1.8V SS ...
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... BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM operations. 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V DESCRIPTION 000 Revision number. def = 001 for 18Mb density for x36 width for x18 width ...
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... V , HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 1 MEG x 18, 512K HSTL, QDRb4 SRAM DD BIT# FBGA BALL 37 10D 10C 40 11D 11B 44 11C 10B 47 ...
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... Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc., 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V Figure 11: 165-Ball FBGA 0.12 C ...
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... Added AC Electrical Characteristics and Operating Conditions table Rev. A, Pub. 4/02, ADVANCE...........................................................................................................................................4/02 • New ADVANCE data sheet 18Mb: 2. HSTL, QDRb4 SRAM DD MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03 2.5V V test conditions for read to write ratio DD Micron Technology, Inc., reserves the right to change products or specifications without notice. 25 ...