MT54V512H18E Micron Semiconductor Products, Inc., MT54V512H18E Datasheet

MT54V512H18E

Manufacturer Part Number

MT54V512H18E

Description

9Mb QDR SRAM, 2.5V Vdd, HSTL , 4-Word Burst,

Manufacturer

Micron Semiconductor Products, Inc.

Datasheet

1.MT54V512H18E.pdf (23 pages)

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9Mb QDR

4-WORD BURST

Features

• 9Mb Density (512K x 18)

• Separate independent read and write data ports

• 100 percent bus utilization DDR READ and WRITE

• High-frequency operation with future migration to

• Fast clock to valid data times

• Full data coherency, providing most current data

• Four-tick burst counter for reduced address

• Double data rate operation on read and write ports

• Two input clocks (K and K#) for precise DDR timing

• Two output clocks (C and C#) for precise flight time

• Single address bus

• Simple control logic for easy depth expansion

• Internally self-timed, registered writes

• +2.5V core and HSTL I/O

• Clock-stop capability

• 13mm x 15mm, 1mm pitch, 11 x 15 grid FBGA

• User-programmable impedance outputs

•

NOTE:

512K x 18, 2.5V V

MT54V512H18E_16_A.fm - Rev. 10/02

OPTIONS

• Clock Cycle Timing

• Configurations

• Package

1. A Part Marking Guide for FBGA devices can be found on Micron’s

‡

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY

with concurrent transactions

operation

higher clock frequencies

frequency

at clock rising edges only

and clock skew matching—clock and data delivered

together to receiving device

package

JTAG boundary scan

Web site ¾

6ns (167 MHz)

7.5ns (133 MHz)

10nx (100 MHz)

512K x 18

165-ball, 13mm x 15mm FBGA

MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS.

http://www.micron.com/numberguide

, HSTL, QDRb4 SRAM

™

SRAM

MT54V512H18E

MARKING

-7.5

-10

-6

0.16µm Process

Table 1:

General Description

nous Pipelined Burst SRAM employs high-speed, low-

power CMOS designs using an advanced 6T CMOS

process.

(double data rate) ports to access the memory array.

The read port has dedicated data outputs to support

READ operations. The write port has dedicated data

inputs to support WRITE operations. This architecture

eliminates the need for high-speed bus turnaround.

Access to each port is accomplished using a common

address bus. Addresses for reads and writes are latched

on alternate rising edges of the K input clock. Each

address location is associated with four 18-bit words

that burst sequentially into or out of the device. Since

data can be transferred into and out of the device on

every rising edge of both clocks (K, K#, C and C#)

memory bandwidth is maximized while simplifying

system design by eliminating bus turnarounds.

MT54V512H18E

MT54V512H18EF-xx

The Micron

The QDR architecture consists of two separate DDR

PART NUMBER

2.5V V

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Valid Part Numbers

QDR

165-Ball FBGA

, HSTL, QDRb4 SRAM

Figure 1:

512K x 18, QDRb4 FBGA

(Quad Data Rate™) Synchro-

DESCRIPTION

512K x 18

ADVANCE

‡

Related parts for MT54V512H18E

MT54V512H18E Summary of contents

Page 1

... V , HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev. 10/02 ‡ PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE FOR EVALUATION AND REFERENCE PURPOSES ONLY AND ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. PRODUCTS ARE ONLY WARRANTED BY MICRON TO MEET MICRON’S PRODUCTION DATA SHEET SPECIFICATIONS. ...

Page 2

... V , HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process burst in progress is ignored. The resulting benefit is that the address rate is kept down to the clock fre- quency even when both buses are 100 percent utilized. READ cycles are pipelined. The request is initiated by asserting R# LOW at K rising edge ...

Page 3

... Vt Source CLK 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V cycles to update the impedance. The user can operate the part with fewer than 1,024 clock cycles, but optimal output impedance is not guaranteed. Clock Considerations The device does not utilize internal phase-locked loops and can therefore be placed into a stopped-clock state to minimize power without lengthy restart times ...

Page 4

... D17 Q16 Q17 R TDO TCK SA NOTE: 1. Expansion address: 2A for 144Mb 2. Expansion address: 3A for 36Mb 3. Expansion address: 9A for 18Mb 4. Expansion address: 10A for 72Mb 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. BW1 BW0 ...

Page 5

... Power Supply: Isolated Output Buffer Supply. Nominally 1.5V. See DC Electrical Characteristics DD and Operating Conditions for range. V Supply Power Supply: GND. SS 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. HSTL, QDRb4 SRAM DD DESCRIPTION Q/2, but may be adjusted to improve system DD Micron Technology, Inc., reserves the right to change products or specifications without notice. 5 ...

Page 6

... No Connect: These signals are not internally connected and may be connected to ground to improve package heat dissipation. NC/SA These balls are reserved for higher-order address bits, respectively. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. HSTL, QDRb4 SRAM DD DESCRIPTION Micron Technology, Inc., reserves the right to change products or specifications without notice. ...

Page 7

... State transitions (R# = LOW (W# = LOW). 3. Read and write state machines can be active simultaneously. Read and write cannot be simultaneously initiated. Read takes precedence. 4. State machine control timing sequence is controlled by K 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V Figure 4: Bus Cycle State Diagram RD always INCREMENT READ READ DOUBLE ...

Page 8

... K clock rising edges is not permitted. The device will ignore the second request. 9. Assumes a WRITE cycle was initiated. BW0# and BW1# can be altered for any portion of the BURST WRITE operation provided that the setup and hold requirements are satisfied. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. ...

Page 9

... AC Electrical Characteristics And Operating Conditions Notes appear following parameter tables; 0°C £ T DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V Absolute Maximum Ratings Voltage on V Relative to V Voltage on V Relative ...

Page 10

... Table 10: Thermal Resistance Note 14; notes appear following parameter tables DESCRIPTION Junction to Ambient (Airflow of 1m/s) Soldered on a 4.25 x 1.125 inch, 4-layer, Junction to Case (Top) Junction to Balls (Bottom) 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process £ +70° MAX unless otherwise noted DD A SYM ³ ...

Page 11

... Control inputs valid to K rising edge Data-in valid rising edge Hold Times K rising edge to address hold K rising edge to control inputs hold K, K# rising edge to data-in hold 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V £ +70°C; +2.4V £ SYM MIN MAX MIN t 6.0 7 ...

Page 12

... I with faster cycle times and greater output loading. Typical value is measured at 7.5ns cycle time. 10. Typical values are measured at V 1.5V, and temperature = 25°C. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process | 11. Operating supply currents and burst mode cur ...

Page 13

... Input pulse levels . . . . . . . . . . . . . . . . . . 0.25V to 1.25V Input rise and fall times . . . . . . . . . . . . . . . . . . . . 0.7ns Input timing reference levels . . . . . . . . . . . . . . . . 0.75V Output reference levels . . . . . . . . . . . . . . . . . . .V ZQ for 50W impedance . . . . . . . . . . . . . . . . . . . . . 250W Output load . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 5 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. HSTL, QDRb4 SRAM DD Output Load Equivalent V Q/2 REF ...

Page 14

... A0, i.e etc. 2. Outputs are disabled (High-Z) one clock cycle after a NOP this example, if address A0 = A1, data Q20 = D10, Q21 = D11. Write data is forwarded immediately as read results. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process Figure 6: READ/WRITE Timing WRITE READ ...

Page 15

... TCK allowable to leave this ball unconnected if the TAP is not used. The ball is pulled up internally, resulting in a logic HIGH level. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. HSTL, QDRb4 SRAM DD TAP Controller State Diagram TEST-LOGIC ...

Page 16

... LSBs are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process Bypass Register To save time when serially shifting data through reg- isters sometimes advantageous to skip certain 0 chips ...

Page 17

... The PRELOAD portion of this instruction is not implemented, so the device TAP controller is not fully 1149.1-compliant. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. HSTL, QDRb4 SRAM DD When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in ...

Page 18

... NOTE and CH refer to the setup and hold time requirements of latching data from the boundary scan register. 2. Test conditions are specified using the load in Figure 10. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V Figure 9: TAP Timing THTL ...

Page 19

... IL AC £ +2.6 and V Power-up During normal operation must not exceed widths less than KHKL (MIN) or operate at frequencies exceeding 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process to 2.5V SS CONDITIONS SYMBOL £ V £ Output(s) disabled, ...

Page 20

... Boundary Scan Table 15: Instruction Codes INSTRUCTION EXTEST IDCODE SAMPLE Z RESERVED SAMPLE/PRELOAD RESERVED RESERVED BYPASS 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 512K x 18 DESCRIPTION 000 Version number. Allows unique identification of SRAM vendor. 1 Indicates the presence register CODE ...

Page 21

... Reserved 30 GND/SA20 31 NC/SA18 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V BALL 10P 11P 11N 10M 11M 11L 10K 11K 11J 11H 10J 11G 11F 10E ...

Page 22

... Micron and the M logo are registered trademarks and the Micron logo is a trademark of Micron Technology, Inc. QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, Micron Technology, Inc., NEC, and Samsung. 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2.5V V Figure 11: 165-Ball FBGA ...

Page 23

... Revision History • New ADVANCE data sheet for 0.16µm process, Rev. A, Pub. 10 /02 .....................................................................10/02 512K x 18, 2. HSTL, QDRb4 SRAM DD MT54V512H18E_16_A.fm - Rev 10/02 0.16µm Process 2. HSTL, QDRb4 SRAM DD Micron Technology, Inc., reserves the right to change products or specifications without notice. 23 ADVANCE 512K x 18 ©2002, Micron Technology Inc. ...

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