MT54V1MH18E Micron Semiconductor Products, Inc., MT54V1MH18E Datasheet - Page 19

• Manufacturer Part Number: MT54V1MH18E
• Description: 18Mb QDR SRAM, 2.5V Vdd, Hstl, 4-Word Burst,
• Manufacturer: Micron Semiconductor Products, Inc.

TAP Instruction Set
Overview
three-bit instruction register. All combinations are
listed in the Instruction Codes table. Three of these
instructions are listed as RESERVED and should not be
used. The other five instructions are described in detail
below.
compliant to the 1149.1 convention because some of
the mandatory 1149.1 instructions are not fully imple-
mented. The TAP controller cannot be used to load
address, data or control signals into the SRAM and
cannot preload the I/O buffers. The SRAM does not
implement the 1149.1 commands EXTEST or INTEST
or the PRELOAD portion of SAMPLE/PRELOAD;
rather, it performs a capture of the I/O ring when these
instructions are executed.
EXTEST
to be executed whenever the instruction register is
loaded with all 0s. EXTEST is not implemented in this
SRAM TAP controller; therefore, this device is not
1149.1-compliant.
tion. When an EXTEST instruction is loaded into the
instruction register, the SRAM responds as if a
SAMPLE/PRELOAD instruction has been loaded.
EXTEST does not place the SRAM outputs (including
CQ and CQ#) in a High-Z state.
IDCODE
32-bit code to be loaded into the instruction register. It
also places the instruction register between the TDI
18Mb: 2.5V V
MT54V1MH18E_16_F.fm – Rev. F, Pub. 3/03
Eight different instructions are possible with the
The TAP controller used in this SRAM is not fully
EXTEST is a mandatory 1149.1 instruction which is
The TAP controller does recognize an all-0 instruc-
The IDCODE instruction causes a vendor-specific,
DD
, HSTL, QDRb4 SRAM
19
and TDO balls and allows the IDCODE to be shifted
out of the device when the TAP controller enters the
Shift-DR state. The IDCODE instruction is loaded into
the instruction register upon power-up or whenever
the TAP controller is given a test logic reset state.
SAMPLE Z
scan register to be connected between the TDI and
TDO balls when the TAP controller is in a Shift-DR
state. It also places all SRAM outputs into a High-Z
state.
SAMPLE/PRELOAD
tion. The PRELOAD portion of this instruction is not
implemented, so the device TAP controller is not fully
1149.1-compliant.
is not implemented, putting the TAP into the Update-
DR state while performing a SAMPLE/PRELOAD
instruction will have the same effect as the Pause-DR
command.
BYPASS
instruction register and the TAP is placed in a Shift-DR
state, the bypass register is placed between the TDI
and TDO balls. The advantage of the BYPASS instruc-
tion is that it shortens the boundary scan path when
multiple devices are connected together on a board.
Reserved
reserved for future use. Do not use these instructions.
The SAMPLE Z instruction causes the boundary
SAMPLE/PRELOAD is a 1149.1 mandatory instruc-
Note that since the PRELOAD part of the command
When the BYPASS instruction is loaded in the
These instructions are not implemented but are
2.5V V
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DD
1 MEG x 18, 512K x 36
, HSTL, QDRb4 SRAM
©2003 Micron Technology, Inc.