ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 32

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

JTAG
JTAG: The IEEE1149.1 Joint Test Action Group boundary
scan standard operational codes shown in Table 3 below are
supported. A separate application note is available with
implementation details.
Built in Self Test
Self-test is initiated by resetting the part and loading a given
configuration register set and filter coefficient set. The self-
test replaces the user programmed input with a PN
sequence and calculates a 16 bit signature from the output
data. This signature is compared to a user-provided
signature and the result is provided as a bit in the status
register. The BIST procedure is as follows:
10. The ISL5216-generated signature may be read from
1. Configure the part as described in “Recommended
2. (optional) Load the 16 bit comparison signature into GWA
3. Write 00000000H to F019H to perform a software reset
4. Write 00000001H to GWA F800H to start the first phase
5. Wait until bit 0 of F800H is cleared indicating the first
6. Write 00000000H to F019H to reset all channels again.
7. Write 00000001H to GWA F800H to start the second
8. Wait until bit 0 of F800H is cleared indicating the second
9. If a comparison signature has been supplied (step 2), bit
ISL5216 configuration procedure following a hardware
reset” above.
F80BH bits 15:0. This value will be compared to the
device-calculated signature and reported in the status
register. The device-calculated signature may also be
read and the comparison performed in the user’s
microcontroller.
of all channels.
of the self test.
phase of self test has completed.
phase of the self test.
phase of self test has completed.
12 of the status register (direct read address register 3) is
set to 1 if the signature matches the ISL5216-generated
signature.
GWA F80BH bits 31:16. The user-supplied signature
(step 2) may be also be read back from bits 15:0.
TABLE 3. JTAG OP CODES SUPPORTED
SAMPLE/PRELOAD
INSTRUCTION
BYPASS
EXTEST
IDCODE
INTEST
32
OP CODE
0000
0001
0010
0011
1111
ISL5216
Filter Compute Engine Data RAM Test
The ISL5216 provides read / write access to the data RAM
used by a channel’s filter compute engine. To access the
data RAM for testing, set bit 15 of GWA F800H. Data must
be written to the RAM in Q / I pairs - 24 bit Q first, then 24 bit
I. Q and I samples are written to the RAM using the indirect
addresses shown in the table below (see To Write to the
Internal Registers above for the indirect write procedure).
Reading of the registers may occur in any order. The table
below provides the valid address range in data RAM test
mode. Note that addresses *000H - *6FFH are valid with the
exception of *300H - *3FFH. * = 0, 1, 2, or 3 for channels 0
through 3, respectively. F800H bit 15 must be cleared after
data RAM testing to return to normal operation.
NOTE:
18. Denotes 0, 1, 2 or 3 for channels 0 - 3, respectively.
INDIRECT ADDRESS (Note 18)
*000H
*001H
*002H
*003H
:
*2FEH
*2FFH
*300H - *3FFH
*400H
*401H
*402H
*403H
:
*6FEH
*6FFH
*700H - *7FFH
DATA RAM ADDRESS MAP
Q sample 0
I sample 0
Q sample 1
I sample 1
:
Q sample 767
I sample 767
unused
Q sample 768
I sample 768
Q sample 769
I sample 769
:
Q sample 1535
I sample 1535
unused
DATA