ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 20

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

POSITIONS
28:18
31:29
41:32
44:42
52:45
62:53
BIT
Block-to-Block Step
Coefficient Memory
Round Select
Data Memory
Data Memory
Data Memory
FUNCTION
Destination
Block Start
Block Start
Block Size
20
Destination Field Bit Mapping
28
AGCLFGN AGCLF
AGCLFGN AGC loop gain select. Only applies to Path 1.
AGCLF
Path(1:0)
OS
FB
F(4:0)
31:29
000
001
010
011
100
101
110
111
Provided for use with the coefficient down-shift bits.
Memory block base address, 0-1023, 0-383 are valid for the ISL5216.
44:42
0
1
2
3
4
5
6
7
(modulo addressing is used).
0-255, usually equal to the decimation factor for the FIR in this instruction.
Memory base address of coefficients, 0-1023, 0-511 are valid on the ISL5216.
INSTRUCTION BIT FIELDS (Continued)
Round Select (Add rounding bit at specified location).
2
2
2
2
2
2
2
no rounding.
Block Size.
8
16
32
64
128
256
512
1024
27
Loop gain 0 or 1 if AGCLF bit is set. Set to 0 (1 is a test mode for future chips).
AGC loop filter enable. Only applies to Path 1. The AGC loop is updated with the magnitude
of this sample (Path(1:0) = 01).
Back End Data Routing Path Selection. (see Back End Data Routing figure)
00
01
10
11
Enable output strobe. Setting this bit generates a data ready signal when the data reaches
the output section and starts the serial output sequence (paths 1, 2, 3). If OS is not set,
there will be no output to the outside world from this channel, for that output calculation, but
the data will be loaded into its output holding register (OS would not be set when routing the
data to another back end when cascading channels).
Feedback data path. When set, the magnitude and dphi/dt from the cartesian-to-polar coor-
dinate converter block are routed to the filter compute engine input (magnitude goes to the
I input and dphi/dt goes to the Q input). Provided for discriminator filtering.
Filter select. For data recirculated to the input of the FIR processor by path 0 or from the
cartesian to polar coordinate converter output, these bits tell which filter sequencer step
gets it as an input.
-24
-23
-22
-21
-20
-19
-18
, use this code when downshifting is not used.
Route output to I2 and Q2, bypassing the FIFO and AGC. This path
also routes to next channel FIR input.
Route output back to filter compute engine input to another FIR in the filter chain.
Route output thru the FIFO and AGC to outputs I2 and Q2.
Route output thru the FIFO and AGC to outputs I1 and Q1.
26
Path1
ISL5216
25
Path0
24
OS
DESCRIPTION
23
FB
22
F4
21
F3
20
F2
19
F1
18
F0