ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 4

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

Pin Descriptions
POWER SUPPLY
INPUTS
CONTROL
C(15:0), Cm1
A(15:0), Am1
B(15:0), Bm1
SYNCI0
SYNCI1
SYNCI2
SYNCI
NAME
VCC1
VCC2
ENIA
ENIB
ENIC
ENID
GND
Dm1
CLK
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
TYPE
-
-
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
4
Positive Power Supply Voltage (core), 2.5V ± 0.125
Positive Power Supply Voltage (I/O), 3.3V ± 0.165
Ground, 0V.
Parallel Data Input bus A. Sampled on the rising edge of clock when ENIA is active (low). Am1 has internal
weak pull down.
Parallel Data Input bus B. Sampled on the rising edge of clock when ENIB is active (low). Bm1 has internal
weak pull down.
Parallel Data Input bus C. Sampled on the rising edge of clock when ENIC is active (low). Cm1 has internal
weak pull down.
Parallel Data Input D15 or tuner channel 0 COF.
Parallel Data Input D14 or tuner channel 0 COFSync.
Parallel Data Input D13 or tuner channel 0 SOF.
Parallel Data Input D12 or tuner channel 0 SOFSync.
Parallel Data Input D11 or tuner channel 1 COF.
Parallel Data Input D10 or tuner channel 1 COFSync.
Parallel Data Input D9 or tuner channel 1 SOF.
Parallel Data Input D8 or tuner channel 1 SOFSync.
Parallel Data Input D7 or tuner channel 2 COF.
Parallel Data Input D6 or tuner channel 2 COFSync.
Parallel Data Input D5 or tuner channel 2 SOF.
Parallel Data Input D4 or tuner channel 2 SOFSync.
Parallel Data Input D3 or tuner channel 3 COF.
Parallel Data Input D2 or tuner channel 3 COFSync.
Parallel Data Input D1 or tuner channel 3 SOF.
Parallel Data Input D0 or tuner channel 3 SOFSync.
Parallel Data Input Dm1 for extended floating point input modes. Dm1 has internal weak pull down.
Input enable for Parallel Data Input bus A. Active low. This pin enables the input to the part in one of two
modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input enable for Parallel Data Input bus B. Active low. This pin enables the input to the part in one of two
modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input enable for Parallel Data Input bus C. Active low. This pin enables the input to the part in one of two
modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input enable for Parallel Data Input bus D. Active low. This pin enables the input to the part in one of two
modes, gated or interpolated. In gated mode, one sample is taken per CLK when ENI is asserted.
Input clock. All processing in the ISL5216 occurs on the rising edge of CLK.
Global synchronization input signal. Used to align the processing with an external event or with other ISL5216
or HSP50216 devices. SYNCI can update the carrier NCO, reset decimation counters, restart the filter
compute engine, and restart the output section among other functions. For most of the functional blocks, the
response to SYNCI is programmable and can be enabled or disabled. This signal is connected to all four
channels and is included for backward compatibility with HSP50216 designs.
Synchronization input signal for channel 0. Same functions as SYNCI but connects only to channel 0. This pin
is internally pulled low to allow it to be left unconnected.
Synchronization input signal for channel 1. Same functions as SYNCI but connects only to channel 1. This pin
is internally pulled low to allow it to be left unconnected.
Synchronization input signal for channel 2. Same functions as SYNCI but connects only to channel 2. This pin
is internally pulled low to allow it to be left unconnected.
ISL5216
DESCRIPTION