ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 21

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

POSITIONS
106:105
115:107
117:116
119:118
122:120
104:96
66:64
75:67
84:76
93:85
95:94
BIT
63
Initial Address Offset Initial address offset (to ADDRB). This is the offset from the start address to other end of filter.
Address Offset Step
Coefficient Memory
Memory Reads Per
Coefficient Memory
Number of FIR
Read Address
Memory Read
Data Memory
Data Memory
Data Memory
Pointer Step
FUNCTION
Step Size 1
Step Size 2
FIR Output
Clocks Per
Block Size
Reserved
Reserved
Step Size
Outputs
21
Set to 0
Set to 0.
66:64
0
1
2
3
4
5
6
7
(Modulo addressing can be used, but is usually not needed. If not needed this bit field can always be
set to 7).
Number of FIR outputs (range is 1 to 512, load w/ desired value minus 1).
This is usually equal to the total decimation that follows the filter.
Read address pointer step (for next run). This is usually equal to the filter decimation times the number
of outputs from the instruction.
For symmetric filters, usually equal to -1 x (number of taps -1).
This is based on the number of taps (load with value below minus 1).
Type
Symmetric, even number of taps
Symmetric, odd number of taps
Decimating HBF
Asymmetric
Complex
Resampling
Interpolating HBF
Set to 0 for all but complex FIR, which is set to 1.
(ADDRA) Step size for all but the last tap computation of the FIR.
Set to -2 for HBF, -1 otherwise.
(ADDRA) Step size for last tap computation. Set to -1.
117:116
0
1
2
3
(ADDRB) Step size for opposite end of symmetric filter. Set to +2 for Decimating HBF, to +1 for others
(the B data is not used for asymmetric, resampling, and complex filters).
(ADDRC) Usually set to 1.
122:120
0
1
2
3
4
5
6
7
INSTRUCTION BIT FIELDS (Continued)
Memory Block Size
8
16
32
64
128
256
512
1024
Step size
0
-1
-2
step size value.
Step size
0
1
2
4
8
16
32
64
ISL5216
Value
(taps/2) or floor((taps+1)/2).
(taps+1)/2 or floor((taps+1)/2).
(taps+5)/4.
taps.
taps .
taps/phase (six taps per phase for the ROM’d coefficients provided).
(taps+5)/4-1 .
DESCRIPTION