ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 46

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

P(31:0)
P(31:0)
P(15:0)
P(15:0)
31:22
19:18
17:16
15:0
15:0
N/A
8:7
6:4
2:0
21
20
9
3
Fixed/Floating point
0
1
Floating point mantissa size select bits 0 and 1. See Floating Point Input Mode Bit Mapping Tables for details.
De-multiplex control. These control bits are provided to demultiplex an input data stream comprised of a set of multiplexed data
streams. Up to eight multiplexed data streams can be demultiplexed. These control bits select how many clocks after the ENIx signal
to wait before taking the input sample. ENIx should be asserted for one clock period and aligned with the first channel of the
multiplexed data set. For example, if four streams are multiplexed at half the clock rate, ENIx would align with the first clock period
of the first stream, the second would start two clocks later, the next four clocks after ENIx, etc. The samples are aligned with ENIx
(zero delay) at the input of the input level detector at the next ENIx.
000
111
Interpolated/Gated Mode Select
0
1
Unused. Set to 0.
Set to zero.
1
0
1
0
This bit may also be set low temporarily when free running to stabilize the accumulator data for reading.
Input Level Detector Leak factor, A.
00
01
10
11
Input Level Detector Mode
00
01
10
Input Level Detector Interval
Load with two less than the desired number of input samples. The interval range is 2–65537 input samples.
Writing to this location clears the input level detector accumulator and restarts the interval counter. When the interval counter is done,
bit 1 of the status word (direct register 3) is set.
This 16-bit value can be used as the input to one or more NCO/Mixer/CIC sections or to the input level detector for test or to set the
input to a constant value to minimize power when the channel is not in use.
The ENI signal for this input is either bit 11 in the channel register at IWA *000h or the strobe generated by a write to location GWA
F808h (selected via bit 12 of the channel register at IWA *000h).
TABLE 41. INPUT LEVEL DETECTOR SOURCE SELECT/FORMAT REGISTER (GWA = F804h) (Continued)
Fixed point
Floating point. The 17-bit input bus is divided into 11 to 16 mantissa bits and one to three exponent bits depending on bits 17,
16, 8 and 7. See Floating Point Input Mode Bit Mapping Tables for details.
zero delay
Seven clock periods of delay.
Gated. The input level detector is updated once per clock when ENIx is asserted.
Interpolated. The input level detector is updated every clock. The input is zeroed when ENIx is high.
Ones complement of 16-bit data after formatting.
Unmodified input.
Free run (ignore interval counter).
Stop when interval counter times out.
1
2
2
2
Leaky integrator (Y
Peak detector.
Integrator (bit 20 should be set to 0).
-8
-12
-16
TABLE 42. INPUT LEVEL DETECTOR CONFIGURATION REGISTER (GWA = F805h)
TABLE 43. INPUT LEVEL DETECTOR START STROBE REGISTER (GWA = F806h)
46
n
TABLE 44. µP/TEST INPUT BUS REGISTER (GWA = F807h)
= A*X
n
+ (1-A)*Y
n-1
, where A is the gain selected in bits 19:18).
ISL5216
FUNCTION
FUNCTION
FUNCTION
FUNCTION