ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 10

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

NOTE:
NOTE:
Level Detector
An input level detector is provided to monitor the signal level
on any of the input busses. The input bus, input format, and
the level detection type are programmable (see
Microprocessor Interface section, GWA registers F804h,
F805h and F806h). This signal level represents the wideband
signal from the A/D and is useful for controlling gain /
attenuation blocks ahead of the converter.
The supported monitoring modes are: integrated magnitude
(like the HSP50214 w/o the threshold), leaky integration
(Y
(see GWA = F805h), and peak detection. The measurement
interval can be programmed from 2 to 65537 samples (or
continuous for the leaky integrator and peak detect cases).
The output is 32 bits and is read via the µP interface.
Note that the accumulators in the input level detector are 32
bits wide. This may limit the integration range to as few as
512 samples (for a 42dB exponent range).
12. To select this mode, set IWA *000H / GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 0 respectively.
13. To select this mode, set IWA *000H / GWA F804H bits 17, 16, 8 and 7 to 1, 1, 0 and 1 respectively.
011
X(-1) = 0
X(-1) = 1
000
001
010
n
EXPONENT
EXPONENT
= X
ABSOLUTE
16
n
VALUE
x A + Y
MSB
15-BIT MODE: 15-BIT MANTISSA (15:1), 2-BIT EXPONENT (-1, 0), 18dB MAXIMUM EXPONENT RANGE (Note 12)
16-BIT MODE: 16-BIT MANTISSA (15:0), 1-BIT EXPONENT (-1), 6dB MAXIMUM EXPONENT RANGE (Note 13)
FIGURE 1. INTEGRATED MODE
n-1
0
6
12
18
0
6
GAIN (dB)
GAIN (dB)
x (1-A)) where A = 1, 2
10
2
0, -8, -12, -16
X15
X15
X15
X15
X15
X15
X14
X14
X14
X14
X14
X14
-8
, 2
-12
X13
X13
X13
X13
X13
X13
, or 2
32
-16
X12
X12
X12
X12
X12
X12
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
PIN BIT WEIGHTING TO 16-BIT INPUT MAPPING
ISL5216
X11
X11
X11
X11
X11
X11
X10
X10
X10
X10
X10
X10
Complex Input Mode
In this mode, complex (I/Q) data can be input using two clock
cycles with I input first and Q input second. The ENIx signal
indicates the clock cycle when I is valid. The Q data is taken
on either the next input clock or two clocks after I, as
determined by IWA *000H bit 23. The complex multiply is
done in two clock cycles: I * COS and I * SIN on the first
2
0, -8, -12, -16
16
X9
X9
X9
X9
X9
X9
X
A =
2
16
0, -8, -12, -16
EN
X8
X8
X8
X8
X8
X8
FIGURE 3. LEAKY INTEGRATOR
FIGURE 2. PEAK DETECTOR
A
X7
X7
X7
X7
X7
X7
B
Σ
X6
X6
X6
X6
X6
X6
A > B
X5
X5
X5
X5
X5
X5
Σ
Y
X4
X4
X4
X4
X4
X4
N
R
G
E
= A * X + (1 - A) * Y
R
E
G
EN
X3
X3
X3
X3
X3
X3
32
32
X2
X2
X2
X2
X2
X2
Y
X1
X1
X1
X1
X1
X1
N-1
X0
X0
0
0
0
0