ISL5216 Intersil Corporation, ISL5216 Datasheet - Page 40

• Manufacturer Part Number: ISL5216
• Description: ISL5216 Datasheet
• Manufacturer: Intersil Corporation

P(31:0)
31:29
27:26
25:24
23:22
21:20
19:16
15:12
11:0
28
Set to zero.
Sync polarity
1
0
Reserved, set to zero.
Sync position. This applies to all time slots in the serial output. The Sync programming is associated with the SD1x serial output data
stream (x = A, B, C, or D).
00
01
1X
Reserved, set to zero.
Magnitude output scale factor. The magnitude output of the cartesian to polar coordinate conversion has bits weighted as:
2
The gain in the conversion is 0.82338. When using 16 bits, the range is such that the LSB has a weight of 0.00007 and the maximum
output is 2.32, both after the conversion gain. This corresponds to an I/Q vector length of -83dBFS to +3dBFS. These control bits
add gain (with saturation) for more resolution at the bottom of the scale. A code of 00 passes the magnitude unchanged, 01 shifts
the magnitude up one bit position’ 10 shifts by two positions and 11 shifts up three positions. The resulting bit weights and range
(after conversion gain) for the unsigned numbers are:
Code
00
01
10
11
The upper limits on codes 00 and 01 are the same, but 01 has no leading zero.
Serial data output SD1 routing mask. 0 disables. 1 enables.
Bit
16
17
18
19
Serial data output SD2 routing mask. 0 disables. 1 enables.
Bit
12
13
14
15
Output hold-off delay. This parameter adds additional delay from the output of the filter compute engine to start of the serial output
stream for multiplexing channels. Load with the desired delay (0 = zero, 1 = one, 2 = two, etc.).
(2 1 0.-1 -2 -3 -4 . . . )
Active low (low for one serial clock per word with a sync).
Active high.
Sync is asserted during the serial clock period prior to the first data bit of the serial word (early sync).
Sync is asserted during the clock period following the last data bit of the word (late sync).
Sync is asserted during the serial clock period of the first data bit of the serial word (coincident sync).
Bit Weights
2 1 0 -1 -2 . . . -11 -12 -13
1 0 -1 -2 -3 . . . -12 -13 -14
0 -1 -2 -3 -4 . . . -13 -14 -15
-1 -2 -3 -4 -5 . . . -14 -15 -16
Enabled Output
Enables the serial output for this channel to pin SD1A.
Enables the serial output for this channel to pin SD1B.
Enables the serial output for this channel to pin SD1C.
Enables the serial output for this channel to pin SD1D.
Enabled Output.
Enables the serial output for this channel to pin SD2A.
Enables the serial output for this channel to pin SD2B.
Enables the serial output for this channel to pin SD2C.
Enables the serial output for this channel to pin SD2D.
40
TABLE 25. SERIAL DATA OUTPUT CONTROL REGISTER (IWA = *014h)
dBFS
+3 to -83
+3 to -89
+1.7 to -95
-4.3 to -101
ISL5216
FUNCTION