dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 13

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
RD
R/W
TA
Signal
Name
Output Tri-stated Read Enable—RD is asserted low during external memory read
Output Tri-stated Read/Write—The timing for this signal is the same as the bus address
Signal
Input
Type
Input
during
Reset
State
Table 1-7 Bus Control Signals (Continued)
cycles. When RD is asserted in late T0/early T1, the data bus signals
(D0–D15) become inputs and an external device is enabled on the
data bus. When RD is deasserted in T3, the data is latched in the
DSP. The signal qualifies A0–A15 and PS/DS. RD is tri-stated when
the DSP is not the bus master. RD can be connected directly to the
OE pin of a ROM or Static RAM.
lines, providing an early write signal. R/W changes in T0 and is high for a
read access and low for a write access. If the external bus is not used
during an instruction cycle, R/W goes high at the next T0.
Transfer Acknowledge—When there is external bus cycle activity,
TA can be used to insert Wait States (WS) in the external bus cycle.
TA is sampled on the leading edge of the clock input. If TA is
sampled high, the bus cycle will end 2T after TA is sampled low,
assuming the Bus Control Register (BCR) is not programmed to
insert its own WS. The number of WS is determined by TA and the
BCR and is equal to the larger of the two determining sources. TA
continues to be sampled as the BCR WS number decrements. If TA
is sampled low, but there are remaining WS required by the BCR,
the bus cycle continues until the BCR requirement is satisfied. If the
BCR requirement is satisfied, but TA has not been sampled low, the
WS continue until 2T after TA is sampled low.
To be sampled high at the start of the bus cycle, TA must be driven
high in T3 on the previous instruction cycle. If TA is sampled low at
T0 of a bus cycle and no WS are specified by the BCR, no WS are
inserted in the external bus cycle.
If there is no external bus activity, the DSP ignores TA.
DSP56167/D, Rev. 1
Signal Description
Signal/Pin Descriptions
Bus Control
1-7