dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 50

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
Host I/O (HI) Timing
HOST I/O (HI) TIMING
V
2-24
DD
Num
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
T = I
cyc = Clock cycle = 1/2 Instruction cycle = 2 T cycle
t
t
HSDL
SUH
= 5.0 V 10%; T
CYC
Host Synchronous Delay
HEN/HACK assertion width
HEN/HACK deassertion width
Minimum cycle time between two HEN assertions for
Consecutive CVR, ICR, ISR reads
Host data input setup time before HEN/HACK deassertion
Host data input hold time after HEN/HACK deassertion
HEN/HACK assertion to output data active from tri-state
HEN/HACK assertion to output data valid
HEN/HACK deassertion to output data tri-stated
Output data hold time after HEN/HACK deassertion
HR/W low setup time before HEN assertion
HR/W low hold time after HEN deassertion
HR/W high setup time to HEN assertion
HR/W high hold time after HEN/HACK deassertion
HA0–HA2 setup time before HEN assertion
HA0–HA2 hold time after HEN deassertion
DMA HACK assertion to HREQ deassertion
DMA HACK deassertion to HREQ assertion
= Host processor data setup time
= Host Synchronization Time Delay
Note: Active low lines should be “pulled up” in a manner consistent with the AC
a. CVR,ICR, ISR Read
b. Read
c. Write
for DMA RXL Read
for DMA TXL Write
for All Other Cases
/ 4
and DC specifications.
J
= –40 to +115˚C; C
Characteristics
1
2,4
Table 2-12 Host I/O Timing
DSP56167/D, Rev. 1
2
L
= 50 pF + 1 TTL load
3
3
t
t
HSDL
HSDL
2T + 30
4T + 30
Min
25
27
27
—
—
—
+ 3T + 4
+ 2T + 4
T
3
9
5
4
4
4
3
0
6
6
4
2T + 35
Max
MOTOROLA
3T
—
—
—
—
—
—
—
24
24
17
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns