dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 90

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Design Considerations
Host Port Usage Considerations
DSP Programmer Considerations
4-14
When reading HF0 and HF1 as an Encoded Pair, the DMA, HF1, HF0, and HCP,
HTDE, and HRDF (refer to DSP56167 User’s Manual , I/O Interface section, Host/
DMA Interface Programming Model for descriptions) status bits are set or cleared by
the host processor side of the interface. These bits are individually synchronized to
the DSP clock.
Note: A potential problem exists when reading status bits HF1 and HF2 as an
• Overwriting the Host Vector—The host programmer should change the Host
• Cancelling a Pending Host Command Exception—The host processor may
Vector register only when the Host Command bit (HC) is clear. This change
will guarantee that the DSP interrupt control logic will receive a stable vector.
elect to clear the HC bit to cancel the Host Command Exception request at any
time before it is recognized by the DSP. Because the Host does not know
exactly when the exception will be recognized (due to exception processing
synchronization and pipeline delays), the DSP may execute the Host
exception after the HC bit is cleared. For these reasons, the HV bits must not
be changed at the same time the HC bit is cleared.
encoded pair, (i.e., the four combinations 00, 01, 10, and 11 each have
significance). A very small probability exists that the DSP will read the status
bits synchronized during transition. The solution to this potential problem is
to read the bits twice for consensus.
DSP56167/D, Rev. 1
MOTOROLA