dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 20

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Signal/Pin Descriptions
Codec
CODEC
1-14
AUX
MIC
SPKP
SPKM
VRAD
VRDA
VDIV
Note:
Signal
Name
The SPKP and SPKM outputs consist of a fully differential driver stage, with each output
having an operating range of 1.0 V
between the differential outputs.
0.35 mA of current which can drive a resistive load of 3 k in series with 15 nF capacitance
Output
Output
Output
Output
Output
Signal
Input
Input
Type
Input
Input
during
Reset
State
Auxiliary Input—This signal is selected as the analog input to the
A/D converter when the INS bit in Codec Control Register 1
(CCR1) is set. Leave this pin floating when the codec is not used.
Microphone Input—This signal is selected as the analog input to
the A/D converter when the INS bit in CCR1 is cleared. Leave this
pin floating when the codec is not used.
Speaker Output 1—This signal is the negative analog output
from the on-chip D/A converter. Leave this pin floating when the
codec is not used. In the codec Power Down mode, this signal
connects internally to VDIV through a high impedance path.
Speaker Output 2—This signal is the positive analog output from
the on-chip D/A converter. Leave this pin floating when the codec
is not used. In the codec Power Down mode, this signal connects
internally to VDIV through a high impedance path.
Voltage Reference Output for A/D— This is the output from the
op-amp buffer in the A/D sections reference voltage generator.
It has a value of 1/2 V
ground internal to the A/D block. Always connect this pin to
ground through two capacitors even when the codec is not used.
In codec Power Down mode, the VRAD signal is tri-stated.
Voltage Reference Output for D/A— This is the output from the
op-amp buffer in the D/A sections reference voltage generator.
It has a value of 1/2 V
ground internal to the D/A block. Always connect this pin to
ground through two capacitors even when the codec is not used.
In codec Power Down mode, the VRDA signal is tri-stated.
Voltage Division Output—This is the input to the op-amp
buffer in the reference voltage generator. It is connected to a
resistor divider network located within the codec block that
provides a voltage equal to 1/2 V
when the codec is not used. This output is not affected by codec
Power Down mode.
Table 1-10 Codec Signals
DSP56167/D, Rev. 1
P
from VRDA. The output op-amp can provide up to
DDA
DDA
Signal Description
. This voltage is used as the analog
. This voltage is used as the analog
DDA
. Leave this pin floating
MOTOROLA