dsp56167 Freescale Semiconductor, Inc, dsp56167 Datasheet - Page 58

• Manufacturer Part Number: dsp56167
• Description: Advance Information 16-bit Digital Signal Processor
• Manufacturer: Freescale Semiconductor, Inc

Specifications
16-Bit Synchronous Serial Interface (SSI) Timing
16-BIT SYNCHRONOUS SERIAL INTERFACE (SSI) TIMING
V
2-32
DD
Num
T = I
SCK = Serial Clock
SFS = Transmit/Receive Frame Sync
i ck = Internal Clock and Frame Sync
x ck = External Clock and Frame Sync
bl = bit length
wl = word length
T
134
135
136
137
138
139
140
141
142
143
144
145
146
150
153
154
155
= 5.0 V 10%; T
S
= SCK/2
CYC
SCK Rising Edge to SFS In (bl) High
SCK Rising Edge to SFS In (bl) Low
SCK Rising Edge to SFS In (wl) High
SCK Rising Edge to SFS In (wl) Low
Data In Setup Time Before SCK Falling Edge
Data In Hold Time After SCK Falling Edge
SCK Rising Edge to SFS Out (bl) High
SCK Rising Edge to SFS Out (wl) High
SCK Rising Edge to SFS Out Low
SCK Rising Edge to Data Out Enable from High
Impedance
SCK Rising Edge to Data Out Valid
SCK Rising Edge to Data Out Invalid
SCK Rising Edge to Data Out High Impedance
SCK Clock Cycle
SCK Clock Rise/Fall Time
SCK Rising Edge to SFS Out (bl) High
SCK Rising Edge to SFS Out (bl) Low
Note: All the timings for the 16-bit SSI are given for a non-inverted serial clock
/ 4
polarity (SCKP = 0 in CRB) and a non-inverted frame sync (FSI = 0 in CRB). If
the polarity of the clock and/or the frame sync have been inverted, all the
timings remain valid by inverting the clock signal SCK and/or the frame sync
SFS in the tables and in the figures.
J
= –40 to +115˚C; C
1
Characteristics
Table 2-16 SSI Timing
DSP56167/D, Rev. 1
L
= 50 pF + 1 TTL load
Min
16.7
3.0
8.5
—
—
—
—
—
—
—
—
—
—
27
—
—
6
60 MHz
T
Max
20.4
20.4
16.0
20.4
16.7
16.7
S
1.2
3.3
—
—
—
21
10
—
10
—
2
Case
x ck
x ck
x ck
x ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
i ck
MOTOROLA
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns