mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet
mc33905s
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mc33905s Summary of contents
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... CAN Bus LIN Bus LIN Bus Figure 1. 33905D Simplified Application Diagram * This document contains certain information on a new product. Specifications and information herein are subject to change without notice. © Freescale Semiconductor, Inc., 2010. All rights reserved. EK SUFFIX (PB-FREE) PCZ33905D3EK/R2 MCZ33905D5EK/R2 PCZ33905S3EK/R2 MCZ33905S5EK/R2 ...
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V BAT CAN Bus V BAT LIN Bus Figure 2. 33905S Simplified Application Diagram V BAT V BAT CAN Bus Figure 3. 33904A Simplified Application Diagram 33904/5 2 33905S (5.0 V/3 Q1* VSUP1 VE VB VBAUX VCAUX ...
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Table 1. Device Variations Vdd output Freescale Part No. voltage PCZ33905D3EK/R2 MCZ33905D5EK/R2 PCZ33905S3EK/R2 MCZ33905S5EK/R2 PCZ33904A3EK/R2 MCZ33904A5EK/R2 Analog Integrated Circuit Device Data Freescale Semiconductor DEVICE VARIATIONS CAN LIN Wake up input / LIN master interface interface(s) 3.3V 2 wake up + ...
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TABLE OF CONTENTS Internal Block Diagram .............................................................................................................................. 5 Pin Connections ........................................................................................................................................ 8 Electrical Characteristics ......................................................................................................................... 12 Maximum Ratings ................................................................................................................................. 12 Static Electrical Characteristics ............................................................................................................ 14 Dynamic Electrical Characteristics ....................................................................................................... 21 Timing Diagrams .................................................................................................................................. 24 Functional Description ............................................................................................................................. 28 Introduction ........................................................................................................................................... ...
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VSUP2 SAFE DBG GND VSENSE I/O-0 I/O-1 CANH SPLIT CANL LIN-TERM1 LIN-1 LIN-TERM2 LIN-2 Analog Integrated Circuit Device Data Freescale Semiconductor INTERNAL BLOCK DIAGRAM VBAUX VCAUX VAUX VSUP1 5 V Auxiliary V Regulator Regulator DD V S2-INT Fail-safe Power Management ...
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INTERNAL BLOCK DIAGRAM VSUP2 SAFE DBG GND VSENSE I/O-0 I/O-1 I/O-3 CANH SPLIT CANL LIN-T LIN 33904/5 6 VBAUX VCAUX VSUP1 VAUX 5 V Auxiliary V Regulator Regulator DD V S2-INT Fail-safe Power Management State Machine Oscillator Analog Monitoring Signals ...
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VSUP2 SAFE DBG GND VSENSE I/O-0 I/O-1 I/O-2 I/O-3 CANH SPLIT CANL Analog Integrated Circuit Device Data Freescale Semiconductor VBAUX VCAUX VAUX VSUP1 5 V Auxiliary V Regulator Regulator DD V S2-INT Fail Safe Power Management State Machine Oscillator Analog ...
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... A functional description of each pin can be found in the Functional Pin Description section beginning on Pin # Pin # Pin # Pin Name 33905D 33905S 33904A 1-3,20- N/A 17, 18, N/C 22,27- 19 30,32- 35,52- VSUP1 VSUP2 33904/5 8 PIN CONNECTIONS MC33905S VB VSUP1 VSUP2 3 30 RXD I/O-3 LIN TXD SAFE 5 28 VDD 5V-CAN 6 27 MISO CANH 7 ...
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Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on Pin # Pin # Pin # Pin Name 33905D 33905S 33904A LIN-T2 or I/O-3 ...
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PIN CONNECTIONS Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on Pin # Pin # Pin # Pin Name 33905D 33905S 33904A I/O-0 ...
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Table 2. 33904/5 Pin Definitions (continued) A functional description of each pin can be found in the Functional Pin Description section beginning on Pin # Pin # Pin # Pin Name 33905D 33905S 33904A TXD 49 30 ...
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ELECTRICAL CHARACTERISTICS MAXIMUM RATINGS Table 3. Maximum Ratings All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings (2) ELECTRICAL RATINGS Supply Voltage at V and ...
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Table 3. Maximum Ratings (continued) All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device. Ratings ESD Capability (1) * AECQ100 Human Body Model - JESD22/A114 (C ...
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V reflect the approximate parameter means at T Characteristic POWER INPUT (5) Nominal DC Voltage Range (6) Extended DC Low ...
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Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ V reflect the approximate parameter means at T Characteristic Notes 5. All parameters in spec (ex: V regulator tolerance Device functional, some parameters could be ...
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ V reflect the approximate parameter means at T Characteristic VOLTAGE REGULATOR FOR CAN INTERFACE SUPPLY, PIN 5 V-CAN Output voltage ...
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Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ V reflect the approximate parameter means at T Characteristic UNDERVOLTAGE RESET AND RESET FUNCTION, RST PIN (CONTINUED) Reset input threshold Low threshold High threshold Reset input hysteresis ...
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ELECTRICAL CHARACTERISTICS STATIC ELECTRICAL CHARACTERISTICS Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ V reflect the approximate parameter means at T Characteristic ANALOG MUX OUTPUT (CONTINUED) Internal reference voltage Current ratio between VDD output & ...
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Table 4. Static Electrical Characteristics (continued) Characteristics noted under conditions 5.5 V ≤ V reflect the approximate parameter means at T Characteristic CAN OUTPUT PINS (CANH, CANL) Bus pins common mode voltage for full functionality Differential input voltage threshold Differential ...
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... V < V < +12 to +35 V SPLIT LIN TERM1, LIN TERM2 LIN-T1, LIN-T2, high side switch drop @ I = -20 mA, V LIN1 AND LIN 2 MC33905D PIN - LIN1 MC33905S PIN (Parameters guaranteed for V Operating Voltage Range Supply Voltage Range Current Limitation for Driver Dominant State Driver ON, V ...
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DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V values noted reflect the approximate parameter means at T Characteristic SPI TIMING SPI operation frequency (MISO cap = 50 pF) SCLK Clock Period SCLK ...
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ELECTRICAL CHARACTERISTICS DYNAMIC ELECTRICAL CHARACTERISTICS Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V values noted reflect the approximate parameter means at T Characteristic STATE DIGRAM TIMINGS Delay for SPI Timer A, Timer B or Timer ...
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Table 5. Dynamic Electrical Characteristics Characteristics noted under conditions 5.5 V ≤ V values noted reflect the approximate parameter means at T Characteristic LIN 1 AND LIN 2 PHYSICAL LAYER: DRIVER CHARACTERISTICS FOR NORMAL SLEW RATE - 20.0 KBIT/SEC ACCORDING ...
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS WCLKH LEAD SCLK T SISU MOSI Undefined T VALID T SOEN MISO TXD 0.3 x VDD RXD Figure 10. CAN Signal Propagation Loop Delay TXD to RXD TXD 0.3 x VDD V ...
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V 10 µF Signal generator 15 pF Figure 12. Test Circuit for CAN Timing Characteristics TXD t BIT t BUS_DOM V LIN_REC 74. SUP REC(MAX) 58. SUP DOM(MAX) LIN 42.2% V SUP TH REC(MIN) ...
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ELECTRICAL CHARACTERISTICS TIMING DIAGRAMS TXD t BIT t BUS_DOM V LIN_REC 77. SUP REC(MAX) 61. SUP DOM(MAX) LIN 38.9% V SUP TH REC(MIN) 25. SUP DOM(MIN) RXD Output of receiving Node 1 t REC_PDF(1) ...
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_REC Figure 16. LIN Wake-up Low Power V Analog Integrated Circuit Device Data Freescale Semiconductor nant l evel T ...
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FUNCTIONAL DESCRIPTION INTRODUCTION The MC33904_5 is the second generation of System Basis Chip, combining: - Advanced power management unit for the MCU, the integrated CAN interface and for additional ICs such as sensors, CAN transceiver. - Built in enhanced high ...
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UNDER-VOLTAGE RESET AND RESET FUNCTION (RST) The RESET pin is an open drain structure with an internal pull-up current source. The low side driver has limited current capability when asserted low, in order to tolerate a short to 5.0V.The Reset ...
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FUNCTIONAL DESCRIPTION FUNCTIONAL PIN DESCRIPTION V BAT D1 S_in VSUP_1 VSENSE S_in R 1k SENSE S_in I/O-0 S-i/o_att S_in I/O-1 DGB (DGB) AND DEBUG MODE The DBG pin has 2 functions: Primary function output used to set ...
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... Device contains zero, one or two LIN interfaces. Analog Integrated Circuit Device Data Freescale Semiconductor . In Low Power MC33904 has no LIN interface. MC33905S (S as Single) DD and MC33905D (D as Dual) contain respectively 1 and 2 LIN interfaces. LIN 1 and LIN 2 terminals are the connection to the LIN sub buses ...
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FUNCTIONAL DEVICE OPERATION MODE AND STATE DESCRIPTION FUNCTIONAL DEVICE OPERATION The device has several operation modes. The transitions and conditions to enter or leave each modes are illustrated in the state diagram. INIT RESET This mode is automatically entered after ...
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The device has two main Low Power Modes: Low Power Mode with VDD off, and Low Power Mode with VDD on. note: Prior to enter in Low Power mode, I/O and CAN wake up flags must be cleared (ref to ...
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FUNCTIONAL DEVICE OPERATION STATE DIAGRAM POWER DOWN V SUP Ext reset RESET start T_ R (1ms or config) Wake-up (1) W/D refresh in closed window or enhanced W/D refresh failure (2) If enable by SPI, prior to enter LP V ...
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SPI” DESCRIPTION: A request is done by a SPI command, the device provide on MISO an unpredictable “random code”. Software must perform a logical change on the code and return it to the device with the new SPI command ...
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FUNCTIONAL DEVICE OPERATION WATCHDOG OPERATION DETAIL SPI OPERATION AND SPI COMMANDS FOR ALL WATCHDOG TYPES. In INIT mode, the W/D type (window, time out, advance and number of SPI commands) is selected using register Init W/D, bits 1, 2 and ...
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FUNCTIONAL BLOCK OPERATION VERSUS MODE Table 6. Device Block Operation for Each State State VDD 5V-CAN Power down OFF OFF Init Reset ON OFF INIT ON OFF Reset ON Keep SPI config Normal Request ON Keep SPI config Normal ON ...
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FUNCTIONAL DEVICE OPERATION ILLUSTRATION OF DEVICE MODE TRANSITIONS. Wake-up from Low Power SUP V (4.5V typ) V DD-UV DD Based on reg configuration 5V-CAN Based on reg configuration VAUX RST INT SPI MODE LP V _OFF ...
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CYCLIC SENSE OPERATION DURING LP MODES This function can be used in both Low Power modes (LP Vdd off and LP Vdd on). Cyclic sense is the periodic activation of I/O-0, to allow biasing of external contact swicthes. The contact ...
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FUNCTIONAL DEVICE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN BEHAVIOR AT POWER UP AND POWER DOWN DEVICE POWER UP: This section describe the device behavior during ramp up, and ramp down of Vsup1, and the flexibility offered mainly by ...
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Vbat Vsup_nominal (ex 12V) VSUP1 Vdd (5V) VDD_UV TH (typ 4.65V) VDD RESET Case 1: “Vdd UV th 4.6V”, with bit Crank =0 (default value) Vbat Vsup_nominal (ex 12V) VSUP1 Vsup_th1 (4.1V) Vdd (5V) VDD_UV TH (typ 4.65V) VDD VDD_UV ...
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FAIL SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN OVERVIEW Fail safe mode is entered when specific fail conditions occur. The “Safe state” condition is defined by the resistor connected at the DGB pin. Safe Mode is entered after ...
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Legend: Failure events RESET Device state: bit 4, INIT W (1) bit 4, INIT W (1) SAFE pin release W/D failure (SAFE high) SPI (3) Vdd low: V < UVTH INIT, Normal ...
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FAIL SAFE OPERATION BEHAVIOR AT POWER UP AND POWER DOWN SAFE Mode A Illustration: The figure below illustrate the event, and consequences when SAFE Mode A is selected via the appropriate debug resistor or SPI configuration. Behavior illustration for safe ...
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SAFE mode B1, B2 and B3 illustration: The figure below illustrates the event, and consequences when SAFE Mode B1 selected via the appropriate debug resistor or SPI configuration. Behavior illustration for safe state B (Rdg > ...
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CAN INTERFACE CAN INTERFACE DESCRIPTION The figure below is a high level schematic of the CAN interface. It consist in a low side driver between CANL and gnd, and high side driver from CANH to 5V-CAN. Two differential receivers are ...
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When the CAN interface is in Normal Mode, the driver has two states: recessive or dominant. The driver state is controlled by the TXD pin. The bus state is reported through the RXD pin. When TXD is high, the driver ...
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CAN INTERFACE CAN INTERFACE DESCRIPTION CAN bus Internal wake-up signal Pattern Wake-up In order to wake-up the CAN interface, the wake-up receiver must receive a series of 3 consecutive valid dominant pulses, by default when the CANWU bit is low. ...
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The figure below illustrate some of the most common ter- minations. SPLIT termination CANH C4 60 SPLIT CAN bus C6 60 CANL C5 ECU connector CANH Figure 31. Typical Application and Bus Termination Options Analog Integrated Circuit Device Data ...
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CAN INTERFACE CAN BUS FAULT DIAGNOSTIC The device includes diagnostic of bus short-circuit to GND, VBAT, and internal ECU 5.0 V. Several comparators are implemented on CANH and CANL lines. These comparators TX Logic Diag Figure 32. CAN Bus Simplified ...
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TXD). The bus dominant clamp circuit will help to determine such failure situation. RX PERMANENT RECESSIVE FAILURE The aim of this detection diagnose an external hardware failure at the ...
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CAN INTERFACE CAN BUS FAULT DIAGNOSTIC TXD TO RXD SHORT CIRCUIT: Principle In case TXD is shorted to RXD during incoming dominant information, RXD is set low. Consequently, the TXD pin is low and drives CANH and CANL into a ...
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The physical interface is dedicated to automotive LIN sub- bus applications. The interface has 20kbps and 10kbps baud rates, and includes as well as a fast baud rate for test and programming modes. It has excellent ESD robustness and immunity ...
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LIN BLOCK LIN OPERATIONAL MODES The LIN block can be awakened from Sleep Mode by detection of LIN bus activity. LIN Bus Activity Detection The LIN bus wake-up is recognized by a recessive to dominant transition, followed by a dominant ...
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SERIAL PERIPHERAL INTERFACE The device is using a 16 bits SPI, with the following arrangement: MOSI, Master Out Slave In bits: • bits 15 and 14 (called C1 and C0) are control bits to select the SPI operation mode (write ...
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SERIAL PERIPHERAL INTERFACE DETAIL OPERATION BITS 15,14 AND 8 FUNCTIONS Table 10 summarizes the various SPI operation, depending upon bit 15, 14 and 8. Table 10. SPI Operations (bits 8, 14 & 15) Control bits MOSI[15-14], C1-C0 Type of Command ...
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REGISTER ADRESS TABLE Table 11 is the list of device registers and their associated address, coded with bits Table 11. Device Registers with Corresponding Address Address MOSI[13-9] Description A4...A0 0_0000 Analog Multiplexer 0_0001 Memory byte A 0_0010 ...
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SERIAL PERIPHERAL INTERFACE DETAIL OPERATION COMPLETE SPI OPERATION Table compiled view of all the SPI capabilities and options. Both MOSI and MISO information are described. Table 12. SPI Capabilities with Options Type of Command Read back of ...
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DETAIL OF CONTROL BITS AND REGISTER MAPPING The following tables contain register bit meaning arranged by register address, from address 0_000 to address 1_0100 MUX AND RAM REGISTERS Table 13. MUX Register MOSI First Byte [15-8] [b_15 b_14] 0_0000 [P/N] ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING INIT REGISTERS Note: these registers can be written only in INIT mode Table 15. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode) MOSI First ...
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Table 16. Initialization Watchdog Registers, INIT W/D (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0110 [P/N] bit 110 P WD2INT Default state 0 Condition for default Bit b7 ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 17. Initialization LIN and I/O registers, INIT LIN I/O (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_0111 [P/N] bit 7 01 ...
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Table 18. Initialization Miscellaneous Functions, INIT MISC (note: register can be written only in INIT mode) MOSI First Byte [15-8] [b_15 b_14] 0_1000 [P/N] bit 7 01 01_ 000 P LPM w RND Default state 0 Condition for default Bit ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING .SPECIFIC MODE REGISTER Table 19. Specific Mode Register, SPE_MODE MOSI First Byte [15-8] [b_15 b_14] 01_001 [P/N] bit 7 01 01_ 001 P Sel_Mod[1] Default state 0 Condition for default ...
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TIMER REGISTERS Table 20. Timer Register A, Low Power Vdd over current & Watchdog Period Normal mode, TIM_A MOSI First Byte [15-8] [b_15 b_14] 01_010 [P/N] bit 7 01 01_ 010 P I_mcu[2] Default state 0 Condition for default b7 ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 22. Timer Register C, Watchdog LP Mode or Flash Mode and Forced Wake-up Timer, TIM_C MOSI First Byte [15-8] [b_15 b_14] 01_100 [P/N] bit 7 01 01_ 100 P ...
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WATCHDOG AND MODE REGISTERS Table 24. Watchdog refresh register, W/D MOSI First Byte [15-8] [b_15 b_14] 01_101 [P/N] bit 7 01 01_ 101 P 0 Default state 0 Condition for default Notes 24. The Simple Watchdog Refresh command is in ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Prior to enter in LP Vdd Vdd OFF, the wake up flags must be cleared or read. This is done by the following SPI commands: 0xE100 and ...
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CAN, I/O, INT AND LIN REGISTERS (25) Table 30. REGULATOR register, REG MOSI First Byte [15-8] [b_15 b_14] 01_111 [P/N] bit 7 01 01_ 111 P V [1] AUX Default state 0 Condition for default POR Bits V [1], ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 31. CAN Register, CAN MOSI First byte [15-8] [b_15 b_14] 10_000 [P/N] bit 7 01 10_ 000P CAN mod[1] Default state 1 Condition for default note Bits CAN mod[1], ...
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Table 32. I/O Register, I/O MOSI First byte [15-8] [b_15 b_14] 10_001 [P/N] bit 7 01 10_ 001P I/O-3 [1] Default state 0 Condition for default Bits I/O-3 [1], I/O-3 [0] - I/O-3 terminal operation b7 b6 I/O-3 driver disable, ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 33. INT Register, INT MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] bit 7 01 10_ 010P CAN failure Default state 0 Condition for default Bits CAN failure - ...
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Table 34. LIN 1 Register, LIN1 MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] bit 7 01 10_ 011P LIN mode[1] Default state 0 Condition for default Bits LIN mode [1], LIN mode [0] - LIN 1 interface mode control, ...
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SERIAL PERIPHERAL INTERFACE DETAIL OF CONTROL BITS AND REGISTER MAPPING Table 35. LIN 2 Register, LIN2 MOSI First byte [15-8] [b_15 b_14] 10_010 [P/N] bit 7 01 10_ 100P LIN mode[1] Default state 0 Condition for default Bits LIN mode ...
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DESCRIPTION The table below is the summary of the device flags, I/O real time level and device Identification. They are obtained using the following commands. This command is composed of the following: Table 36. Device Flag, I/O real time and ...
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SERIAL PERIPHERAL INTERFACE FLAGS Table 37. Flag Descriptions Flag Vaux_low Description Reports that V Set / Reset condition Set: V Vaux_over- Description Report that current out of V current Set / Reset condition Set: Current above threshold for t >100μs. ...
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Table 37. Flag Descriptions Flag CAN Over- Description Report that the CAN current is above CAN over current threshold. current Set / Reset condition Set: CAN current above threshold. Reset: current below threshold and flag read (SPI) CAN_UF Description Report ...
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SERIAL PERIPHERAL INTERFACE FLAGS Table 37. Flag Descriptions Flag FWU Description Report that wake up source is Forced Wake Up Set / Reset condition Set: after Forced Wake Up detected. Reset: Flag read (SPI) INT service Description Report that INT ...
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Table 37. Flag Descriptions Flag LIN 1 Description Report that the LIN1 or LIN 2 interface has reach over temperature threshold. Over-temp Set / Reset condition Set: LIN1 /LIN2 thermal sensor above threshold. Reset: sensor below threshold and flag read ...
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TYPICAL APPLICATIONS V BAT D1 V SUP 22uF 100nF (26) >1uF 1k V BAT 22k 100nF V SUP 100nF 60 4.7nF 60 CAN BUS VSUP1/2 1.0 k 1.0 k LIN BUS 1 option 2 option 1 VSUP1/2 1.0 k 1.0 ...
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V BAT D1 V SUP 22uF 100nF (27) >1uF 1k V BAT 22k 100nF V SUP 100nF V SUP 60 4.7nF 60 CAN BUS VSUP1/2 1.0 k 1.0 k LIN BUS 1 option 2 option 1 Notes 27. Cap > ...
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TYPICAL APPLICATIONS V BAT D1 V SUP 22uF 100nF (28) >1uF 1k V BAT 22k 100nF 1k V SUP 100nF V BAT 22k 1k V SUP 100nF 60 60 CAN BUS Notes 28. Cap > 10uF required to pass EMC ...
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The following figure illustrates the application case where 2 reverse battery diodes can be used for optimization of the filtering and buffering capacitor at the VDD pin. This allows using a minimum value capacitor at the V guarantee reset free ...
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PACKAGING SOIC 32 PACKAGE DIMENSIONS For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below. 33904/5 84 PACKAGING SOIC 32 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D ...
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Analog Integrated Circuit Device Data Freescale Semiconductor EK SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D PACKAGING SOIC 32 PACKAGE DIMENSIONS 33904/5 85 ...
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PACKAGING SOIC 32 PACKAGE DIMENSIONS 33904 SUFFIX (PB-FREE) 32-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10556D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor ...
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Analog Integrated Circuit Device Data Freescale Semiconductor SOIC 54 PACKAGE DIMENSIONS EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D PACKAGING SOIC 54 PACKAGE DIMENSIONS 33904/5 87 ...
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PACKAGING SOIC 54 PACKAGE DIMENSIONS 33904 SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D Analog Integrated Circuit Device Data Freescale Semiconductor ...
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Analog Integrated Circuit Device Data Freescale Semiconductor EK SUFFIX (PB-FREE) 54-PIN SOIC WIDE BODY EXPOSED PAD 98ASA10506D REVISION D PACKAGING SOIC 54 PACKAGE DIMENSIONS 33904/5 89 ...
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REVISION HISTORY REVISION DATE DESCRIPTION OF CHANGES 11/2009 • Initial Release 1.0 • Updated LIN 2.0 to LIN 2.1 throughout document 1/2010 2.0 • Changed Pin • Changed Pin VBASE to VB • Added note to Simplified ...
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... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2010. All rights reserved. ...