mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 60

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

INIT REGISTERS
60
33904/5
SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 15. Initialization Regulator Registers, INIT REG (note: register can be written only in INIT mode)
Note: these registers can be written only in INIT mode
[b_15 b_14] 0_0101 [P/N]
b6, b5
b4, b3
b1, b0
MOSI First Byte [15-8]
Bit
Condition for default
b7
00
01
10
11
00
01
10
11
b2
00
01
10
11
0
1
0
1
01 00 _ 101 P
Default state
Cyclic on[1] Cyclic on[0] - Determine if I/O-1 activation time, when cyclic sense function is selected
I/Ox sync
V
I/Ox sync - Determine if I/O-1 is sensed during I/O-0 activation, when cyclic sense function is selected
DDL
bit 7
1
rst[1] VddL rst[0] - Select the V
V
V
DDL
DD
bit 6
0
1600μs (typical value. ref to dynamic parameters for exact value)
200μs (typical value. ref to dynamic parameters for exact value)
400μs (typical value. ref to dynamic parameters for exact value)
800μs (typical value. ref to dynamic parameters for exact value)
rst[1]
rstD[1] V
after V
INT at approx 0.9 V
V
DD
DD
[V
DDL
AUX
bit 5
rises above the V
rstD[0] - Select the Reset terminal low lev duration,
0
I/O-1 sense during I/O-0 activation
rst[0]
5/3] - Select Vauxilary output voltage
DD
Reset at approx 0.9 V
Reset at approx 0.9 V
Reset at approx 0.7 V
Under-voltage threshold, to activate Reset terminal and/or INT
I/O-1 sense anytime
V
Description
V
MOSI Second Byte, bits 7-0
DD
AUX
V
DD
bit 4
AUX
rstD[1]
10ms
20ms
0
1ms
5ms
, Reset at approx 0.7 V
= 3.3V
DD
= 5
under-voltage threshold
POR
V
DD
DD
DD
DD
bit 3
.
.
rstD[0]
0
DD
Analog Integrated Circuit Device Data
V
AUX
bit 2
0
5/3
Freescale Semiconductor
Cyclic on[1]
bit 1
0
Cyclic on[0]
bit 0
0