mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 70

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

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SERIAL PERIPHERAL INTERFACE
DETAIL OF CONTROL BITS AND REGISTER MAPPING
Table 31. CAN Register, CAN
[b_15 b_14] 10_000 [P/N]
MOSI First byte [15-8]
b7 b6
b5 b4
Bits
Condition for default
00
01
10
11
00
01
10
11
b3
b0
0
1
0
1
01 10_ 000P
Default state
CAN mod[1], CAN mod[0] - CAN interface mode control, wake-up enable / disable
CAN interface in Sleep Mode, CAN wake-up disable.
CAN interface in receive only mode, CAN driver disable.
CAN interface is in Sleep Mode, CAN wake-up enable. In device low power mode,
CAN wake-up is reported by device wake-up. In device normal mode, CAN wake-up reported by INT.
CAN interface in transmit and receive mode.
Slew[1] Slew[0] - CAN driver slew rate selection
FAST
MEDIUM
SLOW
SLOW
Wake-up 1/3 - Selection of CAN wake-up mechanism
3 dominant pulses wake-up mechanism
Single dominant pulse wake-up mechanism
CAN INT - Select the CAN failure detection reporting
Select INT generation when a bus failure is fully identified and decoded (i.e after 5 dominant pulses on TxCAN)
Select INT generation as soon as a bus failure is detected, event if not fully identified
CAN mod[1]
bit 7
1
note
CAN mod[0]
bit 6
0
Slew[1]
bit 5
0
POR
Description
MOSI Second Byte, bits 7-0
Slew[0]
bit 4
0
Wake up 1/3
bit 3
POR
0
Analog Integrated Circuit Device Data
bit 2
-
-
Freescale Semiconductor
bit 1
-
-
CAN int
POR
bit 0
0