mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 69

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

.REGULATOR, CAN, I/O, INT AND LIN REGISTERS
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 30.
Notes
25.
[b_15 b_14] 01_111 [P/N]
b7 b6
b4 b3
MOSI First Byte [15-8]
Bits
Condition for default
00
01
10
11
00
01
10
11
b2
b1
b0
0
1
0
1
0
1
The first time the device is set in Normal mode, the CAN is in Sleep wake-up enable (10). The next time the device is set in Normal
mode, the CAN state is controlled by the bit 7 and bit6 states.
01 01_ 111 P
Default state
(25)
V
Regulator OFF
Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags not reported. V
detected after 1.0ms blanking time.
Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags active. V
1.0ms blanking time.
Regulator ON. Under-voltage (UV) and Over-current (OC) monitoring flags active. V
25μs blanking time.
5V-can[1], 5V-can[0] - 5V-CAN regulator control
Regulator OFF
Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags not reported.
Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active.
Regulator ON. Thermal protection active. Under-voltage (UV) and Over-current (OC) monitoring flags active. 5V-CAN disable
in case UV or UV detected after 25μs blanking time.
V
External V
External V
V
Disable the automatic activation of the external ballast
Enable the automatic activation of the external ballast, if V
V
Disable Usage of Low Power V
Enable Usage of Low Power V
REGULATOR register, REG
AUX
DD
DD
DD
bal en - Control bit to Enable the V
bal auto - Control bit to automatically Enable the V
off en - Control bit to allow transition into Low Power V
[1], V
DD
DD
AUX
ballast disable
ballast Enable
[0] - Vauxilary regulator control
V
bit 7
AUX
0
[1]
POR
DD
V
DD
AUX
bit 6
0
OFF Mode
OFF Mode
[0]
DD
external ballast transistor
bit 5
N/A
-
DD
Description
5V-can[1]
MOSI Second Byte, bits 7-0
DD
bit 4
external ballast transistor, if V
DD
0
> typ 60mA
OFF Mode (to prevent V
POR
DETAIL OF CONTROL BITS AND REGISTER MAPPING
5V-can[0]
bit 3
0
AUX
AUX
V
DD
disable in case UV or UV detected after
disable in case UV or UV detected after
DD
bit 2
N/A
DD
bal en
SERIAL PERIPHERAL INTERFACE
AUX
turn OFF)
is > typ 60mA
disable in case UV or UV
V
DD
bit 1
N/A
bal auto
V
DD
bit 0
N/A
off en
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