mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 71

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mc33905s

Manufacturer Part Number
mc33905s
Description
System Basis Chip Gen2 With High Speed Can And Lin Interface
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Analog Integrated Circuit Device Data
Freescale Semiconductor
Table 32. I/O Register, I/O
[b_15 b_14] 10_001 [P/N]
b7 b6
b5 b4
b3 b2
b1 b0
MOSI First byte [15-8]
Bits
Condition for default
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
01 10_ 001P
Default state
I/O-3 [1], I/O-3 [0] - I/O-3 terminal operation
I/O-3 driver disable, Wake-up capability disable
I/O-3 driver disable, Wake-up capability enable.
I/O-3 High Side driver enable.
I/O-3 High Side driver enable.
I/O-2 [1], I/O-2 [0] - I/O-2 terminal operation
I/O-2 driver disable, Wake-up capability disable
I/O-2 driver disable, Wake-up capability enable.
I/O-2 High Side driver enable.
I/O-2 High Side driver enable.
I/O-1 [1], I/O-1 [0] - I/O-1 terminal operation
I/O-1 driver disable, Wake-up capability disable
I/O-1 driver disable, Wake-up capability enable.
I/O-1 Low Side driver enable.
I/O-1 High Side driver enable.
I/O-0 [1], I/O-0 [0] - I/O-0 terminal operation
I/O-0 driver disable, Wake-up capability disable
I/O-0 driver disable, Wake-up capability enable.
I/O-0 Low Side driver enable.
I/O-0 High Side driver enable.
I/O-3 [1]
bit 7
0
I/O-3 [0]
bit 6
0
I/O-2 [1]
bit 5
0
Description
MOSI Second Byte, bits 7-0
I/O-2 [0]
bit 4
0
POR
DETAIL OF CONTROL BITS AND REGISTER MAPPING
I/O-1 [1]
bit 3
0
I/O-1 [0]
bit 2
0
SERIAL PERIPHERAL INTERFACE
I/O-0 [1]
bit 1
0
I/O-0 [0]
bit 0
0
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