mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 40

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mc33905s

Manufacturer Part Number
mc33905s
Description
System Basis Chip Gen2 With High Speed Can And Lin Interface
Manufacturer
Freescale Semiconductor, Inc
Datasheet
DEVICE POWER UP:
and ramp down of Vsup1, and the flexibility offered mainly by
the Crank bit and the 2 Vdd undervoltage reset thresholds.
DEVICE POWER DOWN
Vsup1 ramp down, based on Crank bit configuration, and Vdd
undervoltage reset selection.
Crank bit reset (INIT W/D register, bit 0 =0):
enters in Reset mode due to Vdd Under Voltage condition
40
33904/5
FUNCTIONAL DEVICE OPERATION
BEHAVIOR AT POWER UP AND POWER DOWN
This section describe the device behavior during ramp up,
D1
The figures below illustrate the device behavior during
Bit 0 = 0 is the default state for this bit.
During Vsup ramp down, Vdd remain ON until device
V
VSUP1
BAT
MC33905
Gnd
VDD
BEHAVIOR AT POWER UP AND POWER DOWN
Figure 22. Vdd start up versus Vsup1 tramp
I_VDD
VSUP1
VDD
RESET
Vsup_th1
Vsup1 ramp up. As the Crank bit is by default set to 0, Vdd is
enable when Vsup1 is above Vsup th 1 parameters.
(Vdd < 4.6V or Vdd < 3.2V typ, threshold selected by SPI).
When device is in Reset, if Vsup is below “Vsup_th1”, Vdd is
turned OFF.
Crank bit set (INIT W/D register, bit 0 =1):
remains ON until device detects a POR and set BATfail. This
occurs for a Vsup approx 3V.
Vsup slew rate
The figures below illustrate the device behavior during
The bit 0 is set by SPI write. During Vsup ramp down, Vdd
VDD_off
VDD_start up
10% VDD_start up
90% VDD_start up
Analog Integrated Circuit Device Data
1ms
VDD_UV TH (typ 4.65V)
Vsup_nominal (ex 12V)
Freescale Semiconductor
Vdd nominal (ex 5V)

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