mc33905s Freescale Semiconductor, Inc, mc33905s Datasheet - Page 36

• Manufacturer Part Number: mc33905s
• Description: System Basis Chip Gen2 With High Speed Can And Lin Interface
• Manufacturer: Freescale Semiconductor, Inc

DETAIL SPI OPERATION AND SPI COMMANDS
FOR ALL WATCHDOG TYPES.
and number of SPI commands) is selected using register Init
W/D, bits 1, 2 and 3. The W/D period is selected via TIM_A
register. The W/D period selection can also be done in
Normal mode or in Normal Request mode.
Request mode to Normal mode is done via a single W/D
refresh command (SPI 0x 5A00).
depends upon the W/D type selected in INIT mode. They are
detailed in the paragraph below:
Simple W/D:
within the W/D period if the time out W/D operation is
selected (INIT-W/D register, bit 1 WD N/Win =0).
period) if the Window Watchdog operation was selected
(INIT-W/D register, bit 1 WD N/Win =1).
Normal mode using the 0x5A00 command), RND code must
be read using SPI command 0x1B00. Device returns on
MISO second byte the RND code. The full 16 bits MISO is
called 0x XXRD. RD is the complement of the RD byte.
Advance Watchdog, refresh by 1 SPI command:
command device returns on MISO a new Random Code. This
new random code must be inverted and send along with the
next refresh command and so on.
operation was selected.
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FUNCTIONAL DEVICE OPERATION
WATCHDOG OPERATION
In INIT mode, the W/D type (window, time out, advance
Transition from INIT mode to Normal Mode or from Normal
While in Normal mode, the W/D refresh command
refresh commands is 0x5A00. It can be send any time
It must be send in the open window (second half of the
Advance Watchdog:
The first time device enters in Normal mode (entry on
The refresh command is 0x5ARD. During each refresh
It must be done in the open window if the Window
Advance Watchdog, refresh by 2 SPI commands:
second is 0x5Aw2. Byte w1 contains the first 4 inverted bits
of the RD byte plus the last 4 bits equal to zero. Byte w2
contains 4 bits equal to zero plus the last 4 inverted bits of the
RD byte.
MISO a new Random Code. This new random code must be
inverted and send along with the next 2 refresh commands
and so on.
the Window operation was selected.
Advance Watchdog, refresh by 4SPI commands:
0x5Aw2, the third is 0x5Aw3 and the last is 0x5Aw4.
the last 6 bits equal to zero.
inverted bits of the RD byte plus 4 bits equal to zero.
inverted bits of the RD byte plus 2 bits equal to zero.
inverted bits of the RD byte.
a new Random Code. This new random code must be
inverted and send along with the next 4 refresh commands.
the Window operation was selected.
PROPER RESPONSE TO INT
the INT in a timely manner: Access of the INT register is done
within 2 watchdog periods. Such feature must be enabled by
SPI via the INIT WD register bit 7
The refresh command is splitted in 2 SPI commands.
The first partial refresh command is 0x5Aw1, and the
During this second refresh command device return on
The second command must be done in the open window if
The refresh command is splitted in 4 SPI commands.
The first partial refresh command is 0x5Aw1, the second is
Byte w1 contains the first 2inverted bits of the RD byte plus
Byte w2 contains 2 bits equal to zero plus the next 2
Byte w3 contains 4bits equal to zero plus the next 2
Byte w4 contains 6bits equal to zero plus the next 2
During this fourth refresh command device return on MISO
The fourth command must be done in the open window if
A device detect, that upon an INT, the software handles
Analog Integrated Circuit Device Data
Freescale Semiconductor