lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 10

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
lower limit. Limit register loading is
discussed in the LF Interface
Vertical Filter
The vertical filter is designed to filter
a digital image in the vertical dimen-
sion. It is a FIR filter which can be
configured to have as many as 8-taps.
Line Buffers
There are seven on-chip line buffers.
The maximum delay length of each
line buffer is 3076 cycles and the mini-
mum is 4 cycles. Configuration Reg-
ister 2 (CR
length of the line buffers. The line
buffer length is equal to the value of
CR
the line buffer length to 4. A value of
3072 for CR
to 3076. Any values for CR
than 3072 are not valid.
The line buffers have two modes of
operation: delay mode and recirculate
mode. Bit 0 of Configuration Register
3 determines which mode the line buf-
fers are in. In delay mode, the data
input to the line buffer is delayed by
an amount determined by CR
recirculate mode, the output of the
line buffer is routed back to the input
of the line buffer allowing the line
buffer contents to be read multiple
times.
Bit 1 of Configuration Register 3
allows the line buffers to be loaded in
parallel. When Bit 1 is “1”, the input
register (DIN
buffers in parallel. This allows all
the line buffers to be preloaded with
data in the amount of time it normally
takes to load a single line buffer.
VSHEN enables or disables the load-
ing of data into the line buffers when
the device is in Dimensionally Sepa-
rate Mode (see the VSHEN section for
a full discussion). When in Orthogo-
nal Mode, VSHEN also enables or dis-
ables the loading of data into the input
register (DIN
reverse I/D Registers.
2
plus 4. A value of 0 for CR
2
) determines the delay
2
sets the line buffer length
11-0
11-0
) loads all seven line
) and the forward and
2
TM
greater
2
. In
section.
2
sets
It is important to note that in Orthogo-
nal Mode, either HSHEN or VSHEN
can disable the loading of data into the
input register (DIN
and line buffers. Both must be active
to enable data loading in Orthogonal
Mode.
Interleaved Data
The vertical filter is capable of han-
dling interleaved data. The number
T
T
T
T
ABLE
ABLE
ABLE
ABLE
BITS
BITS
BITS
BITS
11-0
11-2
11-2
3-2
0
1
4
0
1
0
1
4. C
5. C
6. C
7. C
FUNCTION
HV Filter Mode
HV Direction
Orthogonal Kernel Size
Limit Register Load Control
FUNCTION
Line Buffer Length
FUNCTION
Line Buffer Mode
Line Buffer Load
Reserved
FUNCTION
Vertical Limit Enable
Horizontal Limit Enable
Reserved
ONFIGURATION
ONFIGURATION
ONFIGURATION
ONFIGURATION
10
11-0
Horizontal / Vertical Digital Image Filter
), I/D Registers,
R
R
R
R
EGISTER
EGISTER
EGISTER
EGISTER
DESCRIPTION
0 : Orthogonal Mode
1 : Dimensionally Separate
0 : Horizontal to Vertical
1 : Vertical to Horizontal
00 : 3-3 Kernel
01 : 5-5 Kernel
10 : 7-7 Kernel
11 : Not Used
0 : Limit Registers Always Enabled
1 : Limit Registers Under Shift Enable Cont
DESCRIPTION
See Line Buffer Description Section
DESCRIPTION
0 : Delay Mode
1 : Recirculate Mode
0 : Normal Load
1 : Parallel Load
Must be set to “0”
DESCRIPTION
0 : Vertical Limiting Disabled
1 : Vertical Limiting Enabled
0 : Horizontal Limiting Disabled
1 : Horizontal Limiting Enabled
Must be set to “0”
of data sets it can handle is deter-
mined by the number of data values
contained in a video line. If the inter-
leaved video line has 3076 data values
or less, the vertical filter can handle
it no matter how many data sets are
interleaved together.
Vertical Rounding
The vertical filter output may be
rounded by adding the contents of
2 – A
3 – A
4 – A
5 – A
rol
Video Imaging Products
DDRESS
DDRESS
DDRESS
DDRESS
202H
203H
204H
205H
9/14/2005-LDS.3310-I
LF3310