lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 5

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
HRSL
HRSL
sixteen user-programmable Round/
Select/Limit registers (RSL registers)
are used in the horizontal Round/
Select/Limit circuitry (RSL circuitry).
A value of 0 on HRSL
RSL register 0. A value of 1 selects
round/select/limit register 1 and so
on. HRSL
edge of CLK (see the horizontal
round, select, and limit sections for a
complete discussion).
VRSL
VRSL
teen user-programmable RSL registers
are used in the vertical RSL circuitry.
A value of 0 on VRSL
RSL register 0. A value of 1 selects
RSL register 1 and so on. VRSL
latched on the rising edge of CLK (see
the vertical round, select, and limit
sections for a complete discussion).
OE — Output Enable
When OE is LOW, DOUT
enabled for output. When OE is
HIGH, DOUT
high-impedance state.
HPAUSE — LF Interface
When HPAUSE is HIGH, the Hor-
izontal LF Interface
sequence is halted until HPAUSE is
returned to a LOW state. This effec-
tively allows the user to load coef-
ficients and Control Registers at a
slower rate than the master clock (see
the LF Interface
discussion).
VPAUSE — LF Interface
When VPAUSE is HIGH, the Vertical
LF Interface
halted until VPAUSE is returned to
a LOW state. This effectively allows
the user to load coefficients and Con-
trol Registers at a slower rate than the
3-0
3-0
3-0
3-0
— Vertical Round/Select/Limit
— Horizontal Round/Select/
determines which of the six-
determines which of the
3-0
Control
Limit Control
TM
is latched on the rising
11-0
loading sequence is
TM
is placed in a
section for a full
TM
3-0
3-0
loading
TM
TM
selects
selects
11-0
Pause
Pause
is
3-0
is
master clock (see the LF Interface
section for a full discussion).
OPERATIONAL MODES
Dimensionally Separate
In Dimensionally Separate Mode, the
horizontal and vertical filters are
cascaded together to form a
two-dimensional image filter (see Fig-
ures 4 and 5). Bit 1 in Configuration
Register 4 determines the cascade
order. If this bit is set to “0”, data on
DIN
F
F
IGURE
IGURE
DIN
11-0
11-0
is fed into the horizontal filter
4. D
5. D
12
DIN
11-0
IMENSIONALLY
IMENSIONALLY
5
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
Horizontal / Vertical Digital Image Filter
12
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
LINE BUFFER
S
S
TM
EPARATE
EPARATE
12
12
HORIZONTAL FILTER
first. The horizontal filter then feeds
data into the vertical filter. If this bit
is set to “1”, data on DIN
into the vertical filter first. The verti-
cal filter then feeds data into the hori-
zontal filter.
Orthogonal
In Orthogonal Mode, the horizontal
and vertical filters are used concur-
rently to implement an orthogonal
kernel on the input data (see Figure
6). The HV Filter can handle kernel
M
M
Video Imaging Products
ODE
ODE
: H
: V
TO
TO
12
HORIZONTAL FILTER
H
V
DOUT
12
11-0
DOUT
11-0
9/14/2005-LDS.3310-I
11-0
LF3310
is fed