lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 4

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
HCEN —
When HCEN is LOW, data on HCA
is latched into the Horizontal Coeffi-
cient Address Register on the rising
edge of CLK. When HCEN is HIGH,
data on HCA
the register’s contents will not be
changed.
VLD — Vertical Coefficient Load
When VLD is LOW, data on VCF
latched into the Vertical LF Interface
on the rising edge of CLK. When
VLD is HIGH, data can not be latched
into the Vertical LF Interface
enabling the LF Interface
input, a HIGH to LOW transition of
VLD is required in order for the input
circuitry to function properly. There-
fore, VLD must be set HIGH immedi-
ately after power up to ensure proper
operation of the input circuitry (see
the LF Interface
cussion).
VCEN — Vertical Coefficient Address
When VCEN is LOW, data on VCA
is latched into the Vertical Coefficient
Address Register on the rising edge
of CLK. When VCEN is HIGH, data
on VCA
ter’s contents will not be changed.
TXFR — Horizontal Filter LIFO
TXFR is used to change which LIFO in
the data reversal circuitry sends data
to the reverse data path and which
LIFO receives data from the forward
data path. When TXFR goes LOW, the
LIFO sending data to the reverse data
path becomes the LIFO receiving data
from the forward data path, and the
LIFO receiving data from the forward
data path becomes the LIFO sending
data to the reverse data path. The
device must see a HIGH to LOW
transition of TXFR in order to switch
LIFOs.
7-0
Transfer Control
is not latched and the regis-
7-0
TM
Horizontal Coefficient
is not latched and
Enable
section for a full dis-
Address Enable
TM
for data
TM
. When
11-0
7-0
7-0
TM
is
HACC — Horizontal Accumulator
When HACC is HIGH, the horizontal
accumulator is enabled for accumula-
tion and the accumulator output reg-
ister is disabled for loading. When
HACC is LOW, no accumulation
is performed and the accumulator
output register is enabled for loading.
HACC is latched on the rising edge of
CLK.
VACC — Vertical Accumulator Control
When VACC is HIGH, the vertical
accumulator is enabled for accumula-
tion and the accumulator output reg-
ister is disabled for loading. When
VACC is LOW, no accumulation
is performed and the accumulator
output register is enabled for loading.
VACC is latched on the rising edge of
CLK.
HSHEN — Horizontal Shift Enable
HSHEN enables or disables the load-
ing of data into the forward and
reverse I/D Registers in the horizontal
filter when the device is in Dimen-
sionally Separate Mode. If the device
is configured such that the horizontal
filter feeds the vertical filter, HSHEN
also enables or disables the loading of
data into the input register (DIN
If the device is configured such that
the vertical filter feeds the horizontal
filter and the vertical limit register
is under shift control, HSHEN also
enables or disables the loading of data
into the vertical limit register in the
vertical Round/Select/Limit circuitry.
In Orthogonal Mode, HSHEN also
enables or disables the loading of data
into the input register (DIN
the line buffers in the vertical filter.
It is important to note that in Orthogo-
nal Mode, either HSHEN or VSHEN
can disable data loading. Both must
be active to enable data loading in
Orthogonal Mode. Also in Orthogo-
nal Mode, the horizontal and vertical
limit registers can not be disabled.
Control
4
Horizontal / Vertical Digital Image Filter
11-0
) and
11-0
).
When HSHEN is LOW, data is loaded
into and shifted through the registers
HSHEN controls and the forward and
reverse I/D Registers on the rising
edge of CLK. When HSHEN is HIGH,
data is not loaded into or shifted
through the registers HSHEN controls
and the I/D Registers, and their con-
tents will not be changed. HSHEN is
latched on the rising edge of CLK.
VSHEN — Vertical Shift Enable
VSHEN enables or disables the load-
ing of data into the line buffers in the
vertical filter when the device is in
Dimensionally Separate Mode. If the
device is configured such that the ver-
tical filter feeds the horizontal filter,
VSHEN also enables or disables the
loading of data into the input register
(DIN
such that the horizontal filter feeds the
vertical filter and the horizontal limit
register is under shift control, VSHEN
also enables or disables the loading
of data into the horizontal limit reg-
ister in the horizontal Round/Select/
Limit circuitry. In Orthogonal Mode,
VSHEN also enables or disables the
loading of data into the input register
(DIN
I/D Registers in the horizontal filter.
It is important to note that in Orthogo-
nal Mode, either HSHEN or VSHEN
can disable data loading. Both must
be active to enable data loading in
Orthogonal Mode. Also in Orthogo-
nal Mode, the horizontal and vertical
limit registers can not be disabled.
When VSHEN is LOW, data is loaded
into and shifted through the registers
VSHEN controls and the line buffers
on the rising edge of CLK. When
VSHEN is HIGH, data is not loaded
into or shifted through the registers
VSHEN controls and the line buffers,
and their contents will not be
changed. VSHEN is latched on the
rising edge of CLK.
Video Imaging Products
11-0
11-0
). If the device is configured
) and the forward and reverse
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LF3310