lf3310 LOGIC Devices Incorporated, lf3310 Datasheet - Page 7

• Manufacturer Part Number: lf3310
• Description: Horizontal / Vertical Digital Image Filter
• Manufacturer: LOGIC Devices Incorporated

DEVICES INCORPORATED
The I/D Registers also facilitate using
decimation to increase the number of
filter taps. Decimation by N is accom-
plished by reading the horizontal fil-
ter’s output once every N clock cycles.
The device supports decimation up to
16:1. With no decimation, the maxi-
mum number of filter taps is sixteen.
When decimating by N, the number of
filter taps becomes 16N because there
are N–1 clock cycles when the hori-
zontal filter’s output is not being read.
The extra clock cycles are used to cal-
culate more filter taps.
When decimating, the I/D Registers
should be set to a length equal to the
decimation factor. For example, when
performing a 4:1 decimation, the I/D
Registers should be set to a length of
four. When not decimating or when
F
F
IGURE
IGURE
Even-Tap, Even-Symmetric
8
8. S
9. I/D R
EVEN-TAP MODE
A
7
ALU
Coefficient Set
6
B
YMMETRIC
5
A
4
EGISTER
ALU
3
B
2
C
COEF 7
COEF 6
OEFFICIENT
1
D
ATA
P
ATHS
only one data set (non-interleaved
data) is fed into the device, the I/D
Registers should be set to a length of
one.
HSHEN enables or disables the load-
ing of data into the forward and
reverse I/D Registers when the device
is in Dimensionally Separate Mode
(see the HSHEN section for a full dis-
cussion). When in Orthogonal Mode,
HSHEN also enables or disables the
loading of data into the input register
(DIN
It is important to note that in Orthogo-
nal Mode, either HSHEN or VSHEN
can disable the loading of data into the
input register (DIN
and line buffers. Both must be active
to enable data loading in Orthogonal
S
ET
11-0
E
Odd-Tap, Even-Symmetric
XAMPLES
) and the line buffers.
7
A
ODD-TAP MODE
Coefficient Set
6
ALU
5
B
4
7
11-0
A
Horizontal / Vertical Digital Image Filter
3
ALU
), I/D Registers,
2
B
1
Delay Stage N 1
Delay Stage N
COEF 7
COEF 6
2
Mode.
I/D Register Data Path Control
The multiplexer in the middle of the
I/D Register data path controls how
data is fed to the reverse data path.
The forward data path contains the
I/D Registers in which data flows
from left to right in the block diagram
in Figure 1. The reverse data path
contains the I/D Registers in which
data flows from right to left. When
the filter is configured for an even
number of taps, data from the last
I/D Register in the forward data path
is fed into the first I/D Register in
the reverse data path (see Figure 9).
When the filter is configured for an
odd number of taps, the data which
will appear at the output of the last
Video Imaging Products
ODD-TAP INTERLEAVE MODE
Even-Tap, Odd-Symmetric
8
A
7
ALU
Coefficient Set
6
B
5
A
4
ALU
3
B
9/14/2005-LDS.3310-I
2
LF3310
COEF 7
COEF 6
1
2