xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 22

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
A
A2-A0
DDRESS
1 1 1
1 1 1
0 0 0
0 0 0
0 0 1
0 1 0
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0
0 0 1
T
ABLE
EMSR
N
FLVL
MCR
MSR
RHR
THR
FCR
SPR
DLM
LCR
LSR
R
DLL
IER
ISR
AME
EG
8: INTERNAL REGISTERS DESCRIPTION.
RD/WR
RD/WR Divisor
RD/WR
RD/WR
RD/WR
RD/WR
R
W
WR
WR
WR
RD
RD
RD
RD
RD
EAD
RITE
/
RX FIFO
RX FIFO
Enabled
Enable
Trigger
Enable
Global
FIFOs
CTS#
B
Pres-
Rsvd
BRG
caler
Error
Input
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
Bit-7
CD#
Int.
IT
0/
0/
-7
RX FIFO
IR Mode
Enabled
ENable
Enable
Trigger
Set TX
THR &
Empty
FIFOs
RTS#
Break
B
Rsvd
Input
Bit-6
Bit-6
TSR
Bit-6
Bit-6
Bit-6
Bit-6
RI#
Int.
IT
0/
0/
-6
16C550 Compatible Registers
Baud Rate Generator Divisor
TX FIFO
Xoff Int..
XonAny
Enable
Source
Trigger
Empty
DSR#
Parity
B
Hyst.
Input
Bit-5
Bit-5
Bit-5
THR
Bit-5
Auto
RTS
Bit-5
Bit-5
Bit-5
INT
bit-3
Set
IT
0/
0/
0/
0/
-5
22
TX FIFO
Lopback
Internal
Source
Enable
Trigger
Enable
Sleep
Mode
Parity
Break
CTS#
B
Even
Input
Hyst.
Bit-4
Bit-4
Bit-4
Bit-4
Auto
RTS
Bit-4
Bit-4
Bit-4
INT
bit-2
RX
IT
0/
0/
0/
-4
S
HADED BITS ARE ENABLED WHEN
Status Int.
OP2#/INT
RX Fram-
ing Error
Modem
Enable
Source
Enable
Enable
Enable
Output
Mode
Parity
B
Delta
DMA
Rsvd
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
Bit-3
CD#
INT
IT
-3
RX Line
Status-
Enable
Source
(OP1#)
Reset
Parity
B
FIFO
Rsvd
Delta
Rsvd
Error
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Bit-2
Stop
INT
Bits
RI#
Int.
RX
TX
IT
-2
Source
Control
Enable
Length
Output
Empty
Reset
DSR#
Count
RTS#
Over-
Rx/Tx
Word
B
FIFO
Error
Delta
FIFO
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
Bit-1
INT
run
TX
Int.
RX
RX
IT
-1
Control
Enable
Source
Enable
EFR B
Length
Output
Ready
FIFOs
DTR#
CTS#
Rx/Tx
Count
B
Word
Delta
FIFO
Bit-0
Bit-0
Data
Bit-0
Bit-0
Data
Bit-0
Bit-0
Bit-0
Bit-0
INT
RX
Int.
RX
xr
IT
-0
IT
-4=1
LCR ≠ 0xBF
FCTR[6]=0
FCTR[6]=1
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
LCR[7] = 0
LCR[7] = 1
C
REV. 2.1.3
OMMENT