xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 34

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
User Programmable Transmit/Receive Trigger Level Register.
TRG[7:0]: Trigger Level Register
These bits are used to program desired trigger levels when trigger Table-D is selected. FCTR bit-7 selects
between programming the RX Trigger Level (a logic 0) and the TX Trigger Level (a logic 1).
This register is accessible when LCR = 0xBF. Note that this register is not identical to the FIFO Level Register
which is located in the general register set when FCTR bit-6 = 1.
FC[7:0]: FIFO Data Count Register
Transmit/Receive FIFO Count. Number of characters in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7] =
0) can be read via this register.
This register controls the XR16C2850 new functions that are not available in ST16C550 or ST16C650A.
FCTR[1:0]: RTS Hysteresis
User selectable RTS# hysteresis levels for hardware flow control application. After reset, these bits are set to
“0” to select the next trigger level for hardware flow control. See
FCTR[2]: IrDa RX Inversion
•
•
FCTR[3]: Auto RS-485 Direction Control
This bit controls the functionality of the RTS# output if HDCNTL# is connected to VCC. If HDCNTL# is
connected to GND, then the RTS# output will function as the RS-485 half-duplex direction control signal.
•
•
FCTR[5:4]: Transmit/Receive Trigger Table Select
See
FCTR[6]: Scratchpad Swap
•
•
4.16
4.17
4.18
Logic 0 = Select RX input as encoded IrDa data (Idle state will be LOW).
Logic 1 = Select RX input as inverted encoded IrDa data (Idle state will be HIGH).
Logic 0 = Standard ST16C550 mode. Transmitter generates an interrupt when transmit holding register
becomes empty and transmit shift register is shifting data out.
Logic 1 = Enable Auto RS485 Direction Control function. The direction control signal, RTS# pin, changes its
output logic state from low to high one bit time after the last stop bit of the last character is shifted out. Also,
the Transmit interrupt generation is delayed until the transmitter shift register becomes empty. The RTS#
output pin will automatically return to a logic low when a data byte is loaded into the TX FIFO.
Logic 0 = Scratch Pad register is selected as general read and write register. ST16C550 compatible mode.
Logic 1 = FIFO Count register (Read-Only), Enhanced Mode Select Register (Write-Only). Number of
characters in transmit or receive FIFO can be read via scratch pad register when this bit is set. Enhanced
Mode Select Register is selected when it is written into.
Table 10
Trigger Level / FIFO Data Count Register (TRG) - Write-Only
FIFO Data Count Register (FC) - Read-Only
Feature Control Register (FCTR) - Read/Write
for more details.
FCTR B
0
0
1
1
IT
-5
T
ABLE
FCTR B
14: T
0
1
0
1
IT
RIGGER
-4
34
Table-A (TX/RX)
Table-B (TX/RX)
Table-C (TX/RX)
Table-D (TX/RX)
T
ABLE
Table 13
S
ELECT
T
ABLE
for more details.
xr
REV. 2.1.3