xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 9

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

xr
REV. 2.1.3
Each UART channel in the 2850 has a set of enhanced registers for control, monitoring and data loading and
unloading. The configuration register set is compatible to those already available in the standard single
16C550 and dual ST16C2550. These registers function as data holding registers (THR/RHR), interrupt status
and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/
LCR), modem status and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/
DLM), and a user accessible scratchpad register (SPR).
Beyond the general 16C2550 features and capabilities, the 2850 offers enhanced feature registers (EMSR,
FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC) that provide automatic RTS and CTS hardware flow
control, Xon/Xoff software flow control, automatic RS-485 half-duplex direction output enable/disable, FIFO
trigger level control, and FIFO level counters. All the register functions are discussed in full detail later in
“Section 3.0, UART INTERNAL REGISTERS” on page
The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t
mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of
the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional
flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is
empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive
FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is
disabled (FCR bit-3 = 0), the 2850 is placed in single-character mode for data transmit or receive operation.
When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or
unloading the FIFO in a block sequence determined by the programmed trigger level. In this mode, the 2850
sets the TXRDY# pin when the transmit FIFO becomes full, and sets the RXRDY# pin when the receive FIFO
becomes empty. The following table shows their behavior. Also see Figures
2.5
2.6
RXRDY# A/B
TXRDY# A/B
P
INS
Channel A and B Internal Registers
DMA Mode
LOW = 1 byte
HIGH = no data
LOW = THR empty
HIGH = byte in THR
(FIFO D
T
ABLE
FCR
BIT
2: T
ISABLED
-0=0
ABLE
)
CSA#
2TXRDY#
1
0
1
0
LOW = at least 1 byte in FIFO
HIGH = FIFO empty
LOW = FIFO empty
HIGH = at least 1 byte in FIFO
T
ABLE
(DMA Mode Disabled)
FCR Bit-3 = 0
1: C
CSB#
AND
1
1
0
0
HANNEL
RXRDY# O
9
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
Channel A and B selected
A
21.
AND
Channel A selected
Channel B selected
FCR B
UART de-selected
UTPUTS IN
B S
F
UNCTION
IT
-0=1 (FIFO E
ELECT
HIGH to LOW transition when FIFO reaches
the trigger level, or timeout occurs.
LOW to HIGH transition when FIFO empties.
LOW = FIFO has at least 1 empty location
HIGH = FIFO is full
FIFO
20
AND
(DMA Mode Enabled)
NABLED
through 25.
DMA M
FCR Bit-3 = 1
)
ODE
XR16C2850