xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 33

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xr16c2850im

Manufacturer Part Number
xr16c2850im
Description
Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
Manufacturer
Exar Corporation
Datasheet

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xr
REV. 2.1.3
EMSR[5:4]: Extended RTS Hysteresis
EMSR[7:6]: Reserved
The FIFO Level Register replaces the Scratchpad Register (during a Read) when FCTR[6] = 1. Note that this
is not identical to the FIFO Data Count Register which can be accessed when LCR = 0xBF.
FLVL[7:0]: FIFO Level Register
This register provides the FIFO counter level for the RX FIFO or the TX FIFO or both depending on EMSR[1:0].
See Table 12
The concatenation of the contents of DLM and DLL gives the 16-bit divisor value which is used to calculate the
baud rate:
See MCR bit-7 and the baud rate table also.
This register contains the device ID (0x12 for XR16C2850). Prior to reading this register, DLL and DLM should
be set to 0x00.
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
4.12
4.13
4.14
4.15
Baud Rate = (Clock Frequency / 16) / Divisor
FIFO Level Register (FLVL) - Read-Only
Baud Rate Generator Registers (DLL and DLM) - Read/Write
Device Identification Register (DVID) - Read Only
Device Revision Register (DREV) - Read Only
for details.
EMSR
B
IT
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
-5
T
ABLE
EMSR
B
IT
13: E
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
-4
XTENDED
FCTR
B
IT
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
33
-1
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
RTS H
FCTR
B
IT
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-0
YSTERESIS
(C
H
HARACTERS
YSTERESIS
RTS#
±16
±24
±32
±40
±44
±48
±52
±12
±20
±28
±36
±4
±6
±8
±8
0
)
XR16C2850

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