xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 31

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

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REV. 2.1.3
LSR[3]: Receive Data Framing Error Tag
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LSR[4]: Receive Break Error Tag
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LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. The THR bit is set to a logic 1 when the last data byte
is transferred from the transmit holding register to the transmit shift register. The bit is reset to logic 0
concurrently with the data loading to the transmit holding register by the host. In the FIFO mode this bit is set
when the transmit FIFO is empty, it is cleared when the transmit FIFO contains at least 1 byte.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and
transmit shift register are both empty.
LSR[7]: Receive FIFO Data Error Flag
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This register provides the current state of the modem interface input signals. Lower four bits of this register are
used to indicate the changed information. These bits are set to a logic 1 whenever a signal from the modem
changes state. These bits may be used for general purpose inputs when they are not used with modem
signals.
MSR[0]: Delta CTS# Input Flag
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MSR[1]: Delta DSR# Input Flag
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MSR[2]: Delta RI# Input Flag
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MSR[3]: Delta CD# Input Flag
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4.9
Logic 0 = No framing error (default).
Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR.
Logic 0 = No break condition (default).
Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the
FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX
input returns to the idle condition, “mark” or HIGH.
Logic 0 = No FIFO error (default).
Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error
or break indication is in the FIFO data. This bit clears when there is no more error(s) in any of the bytes in the
RX FIFO.
Logic 0 = No change on CTS# input (default).
Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on DSR# input (default).
Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on RI# input (default).
Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Logic 0 = No change on CD# input (default).
Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
Modem Status Register (MSR) - Read Only
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2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
XR16C2850