xr16c2850im Exar Corporation, xr16c2850im Datasheet - Page 8

• Manufacturer Part Number: xr16c2850im
• Description: Dual Uart With Tx And Rx Fifo Counters, 128 Bytes Of Fifos And Automatic Rs-485 Half Duplex Control
• Manufacturer: Exar Corporation

XR16C2850
2.97V TO 5.5V DUAL UART WITH 128-BYTE FIFOS
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The 2850 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in
.
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see
function in the device.
The XR16C2850 provides a Device Identification code and a Device Revision code to distinguish the part from
other devices and revisions. To read the identification code from the part, it is required to set the baud rate
generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x12 for the
XR16C2850 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01
means revision A.
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.2
2.3
2.4
1.
CPU Interface
Device Reset
Device Identification and Revision
Channel A and B Selection
Table
16). An active high pulse of longer than 40 ns duration will be required to activate the reset
F
IGURE
U AR T_R ESET
U AR T_C SA#
U AR T_C SB#
U AR T_IN TA
U AR T_IN TB
3.
R XR D YA#
R XR D YB#
TXR D YA#
TXR D YB#
IOW#
IOR #
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
A0
A1
A2
XR16C2850 D
ATA
B
US
I
8
NTERCONNECTIONS
IOR #
IOW#
C SA#
C SB#
R ESET
D 0
D 1
D 2
D 3
D 4
D 5
D 6
D 7
IN TA
IN TB
TXR D YA#
R XR D YA#
TXR D YB#
R XR D YB#
A0
A1
A2
C hannel A
C hannel B
U AR T
U AR T
D TR A#
D SR A#
D TR B#
D SR B#
R TSA#
C TSA#
R TSB#
C TSB#
OP2A#
C D A#
OP2B#
C D B#
GN D
VC C
R IA#
R IB#
TXA
R XA
TXB
R XB
VC C
Serial Interface of R S-
Serial Interface of
R S-232, R S-485
232, R S-485
2750int
Figure
3.
xr
REV. 2.1.3