ch7305 Chrontel, ch7305 Datasheet
ch7305
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ch7305 Summary of contents
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... VREF 201-0000-054 Rev. 1.31, 6/14/2006 General Description The CH7305 is a Display Controller device, which accepts a graphics data stream over one 12-bit wide variable voltage (1.1V to 3.3V) port. The data stream outputs through an LVDS transmitter to an LCD panel. A maximum of 165M pixels per second can be output through a single or dual LVDS link. The LVDS transmitter supports 24-bit panels ...
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... Register Control..................................................................................................................................................14 3.1 Control Registers Index ..................................................................................................................................14 3.2 Control Registers Description.........................................................................................................................15 3.3 Control Registers Description.........................................................................................................................15 3.4 Recommended Settings...................................................................................................................................27 4.0 Electrical Specifications .....................................................................................................................................28 4.1 Absolute Maximum Ratings ...........................................................................................................................28 4.2 Recommended Operating Conditions .............................................................................................................28 4.3 Electrical Characteristics ................................................................................................................................28 4.4 Digital Inputs / Outputs...................................................................................................................................29 4.5 AC Specifications ...........................................................................................................................................29 4.6 Timing Information ........................................................................................................................................30 5.0 Package Dimensions...........................................................................................................................................33 6.0 Revision History .................................................................................................................................................34 2 Table of Contents 201-0000-054 CH7305 Rev. 1.31, 6/14/2006 ...
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... LL2C* 5 LVDD 6 LDC7 7 LDC7* 8 LGND 9 LDC6 10 LDC6* 11 LVDD 12 LDC5 13 LDC5* 14 LGND 15 LDC4 16 LDC4* 201-0000-054 Rev. 1.31, 6/14/2006 Chrontel CH7305 Figure 2: 64 Pin LQFP Package (Top View) CH7305 48 VDDV 47 RESET VREF DVDD 41 SPD 40 SPC 39 CONFIG 38 LPLL_VDD 37 LPLL_CAP 36 LPLL_GND 35 DGND 34 XI ...
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... This pin configures the device ID. Serial Port Clock Input This pin functions as the clock input of the serial port and can operate with inputs from 1.1V ~ 3.3V. The serial port address of the CH7305 is 75h. For more details on CH7305 serial port read/write operations, please refer to AN61. ...
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... H, V and D[11:0] data. If differential clocks are not available, the XCLK* input should be connected to VREF. The clock polarity can be Register 1Ch selected by the MCP control bit ( Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (1.1V to 3.3V) LVDS Supply Voltage (3.3V) LVDS Ground LVDS PLL Supply Voltage (3.3V) LVDS PLL Ground CH7305 ). 5 ...
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... DDR). For the multiplexed data, clock at 2X pixel rate the data applied to the CH7305 is latched with one edge of the clock (also known as single edge transfer mode or SDR). The polarity of the pixel clock can be reversed under serial port control. In single edge transfer modes, the clock edge used to latch data is programmable ...
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... Input Data Formats The CH7305 supports 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on both clock edges clock latching data with a single edge (rising or falling depending on the value of the MCP bit – rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). Received data is formatted and sent through an internal data bus P[23:0] to the LVDS data path ...
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... P1a P1b P0a R0[7] G1[4] R1[7] G0[5] R0[6] G1[3] R1[6] G0[4] R0[5] G1[2] R1[5] G0[3] R0[4] B1[7] R1[4] B0[7] R0[3] B1[6] R1[3] B0[6] G0[7] B1[5] G1[7] B0[5] G0[6] B1[4] G1[6] B0[4] G0[5] B1[3] G1[5] B0[3] 4 YCrCb 8-bit P0b P1a P1b P2a Y0[7] Cr0[7] Y1[7] Cb2[7] Y0[6] Cr0[6] Y1[6] Cb2[6] Y0[5] Cr0[5] Y1[5] Cb2[5] Y0[4] Cr0[4] Y1[4] Cb2[4] Y0[3] Cr0[3] Y1[3] Cb2[3] Y0[2] Cr0[2] Y1[2] Cb2[2] Y0[1] Cr0[1] Y1[1] Cb2[1] Y0[0] Cr0[0] Y1[0] Cb2[0] CH7305 1 RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit) P0b P1a P1b R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] G1[2] R1[5] R0[4] B1[7] R1[4] R0[3] B1[6] R1[3] G0[7] B1[5] G1[7] G0[6] B1[4] G1[6] G0[5] B1[3] G1[5] R0[2] G1[0] R1[2] R0[1] B1[2] R1[1] R0[0] B1[1] R1[0] G0[1] B1[0] G1[1] 3 RGB 5-5-5 (2x8-bit) P0b P1a P1b X G1[5] X R0[7] G1[4] R1[7] R0[6] G1[3] R1[6] R0[5] B1[7] R1[5] R0[4] B1[6] R1[4] R0[3] B1[5] R1[3] G0[7] B1[4] G1[7] G0[6] B1[3] G1[6] P2b P3a ...
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... HSYNC HSYNC VSYNC VSYNC N/A N/A CH7305 18-bit HSYNC VSYNC DE N/A N/A N/A N/A N/A N/A N/A 9 ...
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... Be2 Be2 Be3 Be3 Be4 Be4 Be5 Be5 1 LCTLE HSYNC 1 LCTLF VSYNC 1 LA6RL DE Re0 Re6 Re1 Re7 Ge0 Ge6 CH7305 18-bit Ro0 Ro1 Ro2 Ro3 Ro4 Ro5 Go0 Go1 Go2 Go3 Go4 Go5 Bo0 Bo1 Bo2 Bo3 Bo4 Bo5 HSYNC VSYNC DE ...
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... LDC[7](6) Note: 1. See description for Register 65h. 2.2.3 Dithering The CH7305 has a dither engine that can convert the 24-bit pixel data to 18-bit pixel data for better image quality on 18-bit panels. Maximum pixel rate supported is 165M Pixels / sec. 2.2.4 Power Sequencing The CH7305 conforms to SPWG’s requirements on power sequencing. The timing specification shown in Figure superset of the requirements dictated by the SPWG specification ...
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... The LCD panel can be damaged if HSYNC is absent from the LVDS link. This situation can happen when there is a catastrophic failure in the PC or the graphics system. The CH7305 is designed to prevent damage to the panel under such a failure. If the system fails, the CH7305 does not expect any software instruction from the graphics controller to power down the panel. Detection circuits are used to monitor the three timing signals – ...
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... For further details, please contact Chrontel Applications Group. 2.3 Power Down The CH7305 can be powered down via software control to achieve very low standby current. For a complete description of each individual bit please refer to the appropriate register description in Registers 63h and 76h. 201-0000-054 Rev. 1.31, 6/14/2006 ...
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... Register Control The CH7305 is controlled via a serial port. The serial bus uses only the SC clock to latch data into registers, and does not use any internally generated clocks so that the device can be written to in all power down modes. The device should retain all register values during power down modes. For registers read/write operation, please refer to applications note AN-61 for details ...
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... LPPSD0 LPVCO3 Reserved LDEN1 LDEN0 L2ODA2 L2ODA1 L2ODA0 Reserved Reserved Reserved LPLF1 LPLF0 LPPDN LPLF3 LPPD4 LPPD3 BGLMT5 BGLMT4 BGLMT3 CH7305 74h 75h 78h 73h 71h 71h 66h 66h 76h 78h 66h 78h 76h 76h 72h 72h 66h 64h 64h 66h ...
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... Section 4.5. STEP CLKDETD R/W R/W R R/W R/W R XCMD3 XCMD2 XCMD1 XCMD0 R/W R/W R 201-0000-054 CH7305 Symbol: CDD Address: 14h Reserved Reserved R/W R/W R Symbol: CM Address: 1Ch MCP Reserved XCM R/W R/W R Symbol: IC Address: ...
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... R/W R/W R CH7305 , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK ahead of Data , XCLK behind Data , XCLK behind Data , XCLK behind Data , XCLK behind Data ...
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... When ResetIB is ‘1’ the control registers operate normally. The control registers are also reset at power internally generated power on reset signal. Version ID Register BIT SYMBOL: VID7 VID6 TYPE DEFAULT Register VID is a read only register containing the version ID number of the CH7305 family. Product Number CH7305 Reserved ResetIB ResetDB R/W R/W R ...
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... SYMBOL: DID7 DID6 TYPE DEFAULT Register DID is a read only register containing the device ID number of the CH7305 the state of the CONFIG pin, pin39 (bit 5 of register 4Bh will update accordingly). Product Number CH7305 CH7305 LVDS Power Down BIT SYMBOL: ...
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... BKLEN (bit 5) of the LPMC register enables the panel backlight. BKLEN = 0 => Disable Backlight =1 => Enable Backlight Reserved LA3RL LA6RL R/W R/W R BKLEN LPLEN LPFORC LPLOCK LSYNCEN PANEN R/W R/W R CH7305 Symbol: LVDSE2 Address: 65h LA7RL LCNTLE LCNTLF R/W R/W R Symbol: LPMC Address: 66h R/W R 201-0000-054 Rev ...
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... Data. The entire bit field, TPON[8:0], is comprised of these bits TPON[7:0] plus TPON8 contained in the PST2 Power Sequencing T2 register (Register 68h, bit 7). Refer to Figure 5 and Table 7 in Section 2.2.4. The range 2ms to 512ms in increments of 1ms. 201-0000-054 Rev. 1.31, 6/14/2006 TPON5 TPON4 TPON3 R/W R/W R CH7305 Symbol: PST1 Address: 67h TPON2 TPON1 TPON0 R/W R/W R ...
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... TPOFF8 contained in the Power Sequencing T3 register (Register 69h, bit 7). Refer to Figure 5 and Table 7 in Section 2.2.4. The range is 2ms to 512ms in increments of 1ms R/W R/W R R/W R/W R TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1 R/W R/W R CH7305 Symbol: PST2 Address: 68h R/W R/W R Symbol: PST3 Address: 69h R/W R/W R Symbol: PST4 Address: 6Ah 2 ...
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... TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0 R/W R/W R LPFFD1 LPFFD0 LPFBD3 LPFBD2 LPFBD1 R/W R/W R LPPSD1 LPPSD0 LPVCO3 LPVCO2 LPVCO1 LPVCO0 R/W R/W R CH7305 Symbol: PST5 Address: 6Bh R/W R/W R Symbol: LPFBDC Address: 71h LPFBD0 R/W R/W R Symbol: LPVC ...
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... LVDS Channel 1 is ‘Off’ and 2 is ‘On’ Both LVDS Channel 1 and 2 are ‘On’ R/W R/W R LxODA0 Output Driver Amplitude (mV) 0 305 1 285 0 265 1 245 0 225 1 410 0 370 1 330 CH7305 Symbol: OUTEN Address: 73h LPCP2 LPCP1 LPCP0 R/W R/W R Symbol: LODA Address: 74h R/W R/W R ...
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... Rev. 1.31, 6/14/2006 R/W R/W R LPLF1 LPLF0 LPPDN R/W R/W R LDC[7:4] & LL2C , LL2C* path Power Down Power Down Power On Power On CH7305 Symbol: LST Address: 75h R/W R/W R Symbol: LPD Address: 76h LPPRB LODPDB1 LODPDB0 R/W R/W R LDC[3:0] , LL1C & LL1C* path ...
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... PLL Loop Filter Resistor Value (Ohm) 0 1800 2600 1 1000 0 1 3200 0 21,800 1 42,600 11,000 0 73,200 LPLF3 LPPD4 LPPD3 R/W R/W R R/W R/W R CH7305 Symbol: LVCTL Address: 78h LPPD2 LPPD1 LPPD0 R/W R/W R Symbol: BGLMT Address: 7Fh R/W R/W R 201-0000-054 Rev. 1.31, 6/14/2006 ...
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... Rev. 1.31, 6/14/2006 1280 x 1024 1400 x 1050 ADh A3h A3h ADh ADh ADh C8h DBh DBh F6h F6h F6h ADh AFh AFh 80h 80h 80h 10h 10h 10h CH7305 1600 x 1200 A3h ADh DBh F6h AFh 80h 10h 27 ...
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... LVDS output @ 65 MHz I VDDV (1.8V) current (15pF load) VDDV I Total Power Down Current PD 28 Min -0.5 GND – 0.5 -65 Min 3.1 3.1 3.1 3.1 1.1 = 0°C – 70°C, VDD =3.3V ± 5%) A Min CH7305 Typ Max Units 5.0 VDD + 0.5 Indefinite Sec ° °C 150 °C 150 °C 260 °C 245 °C 225 ...
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... GND-0 0 -0.4mA VDD-0 3.2mA OL Test Condition Min 25 6. < 1.2ns XCLK = XCLK* to 0.5 D[11:0 Vref D[11:0 0.5 Vref to XCLK = XCLK* 50 CH7305 Typ Max Unit 0.4 V VDD + 0 DVDD+0.5 V Vref-0.25 V VDD + 0 0.2 V Typ Max Unit 165 MHz 40 ns ...
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... V SWING 100Ω and 5pF differential load 80% -> 20% V SWING 100Ω and 5pF differential load for single channel operation. Dual channel operation is required for XCLK 201-0000-054 CH7305 Typ Max Unit 453 mV 453 1.375 V 1.375 ...
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... Fall time Jitter peak to peak j Note 1: Maximum jitter with EMI reduction turned off. 201-0000-054 Rev. 1.31, 6/14/2006 0.8 V swing - Figure 7: AC Timing for LVDS Outputs CH7305 V ring +/-20% V swing Differential 0.2 V swing t f Min Typ Max see section 4.6 see section 4.6 see section 4 ...
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... Hold Time: D[11:0 and DE to XCLK, XCLK XCLK & XCLK* rise/fall time w/15pF load t2 D[11:0 & DE rise/fall time w/ 15pF load PIXELS t2 1 VGA Line t2 CH7305 P0a P0b P1a P1b P2a P2b Min Typ Max see Section 4.5 see Section 4.5 1 ...
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... Package Dimensions Table of Dimensions No. of Leads Milli- MIN 12 10 meters MAX 201-0000-054 Rev. 1.31, 6/14/2006 SYMBOL 0.17 1.35 0.05 0.50 0.27 1.45 0.15 Figure 9: 64 Pin LQFP Package CH7305 LEA D CO- PLANARITY H .004 “ 0.45 0.09 0° 1.00 0.75 0.20 7° 33 ...
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... Removed all references to the GOENB and GPIOL bits. Changed pin name of GPIO to CONFIG Renamed GPIO pin to CONFIG Added ordering information Added lead free and take & reel order information Corrected part number of lead free and tape & reel. 201-0000-054 CH7305 Rev. 1.31, 6/14/2006 ...
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... Chrontel, Inc. All Rights Reserved. Printed in the U.S.A. 201-0000-054 Rev. 1.31, 6/14/2006 Disclaimer ORDERING INFORMATION Package Type Number of Pins LQFP, Lead free 64 LQFP, Lead free, 64 Tape&Reel Chrontel 2210 O’Toole Avenue, Suite 100, San Jose, CA 95131-1326 Tel: (408) 383-9328 Fax: (408) 383-9338 www.chrontel.com E-mail: sales@chrontel.com CH7305 Voltage Supply 3.3V 3.3V 35 ...