ch7305 Chrontel, ch7305 Datasheet - Page 7

• Manufacturer Part Number: ch7305
• Description: Ch7305 Single/dual Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
2.1.4
The de-skew feature allows adjustment of the input setup and hold time. The input data D[11:0] can be latched slightly
before or after the latching edge of XCLK depending on the amount of the de-skew. Note that the XCLK is not changed,
only the time at which the data is latched relative to XCLK. The de-skew is controlled using the XCMD[3:0] bits located
in Register 1Dh. The delay t
t
where
The delay is also tabulated in Table 9.
2.1.5
The CH7305 supports 5 different multiplexed data formats, each of which can be used with a 1X clock latching data on
both clock edges, or a 2X clock latching data with a single edge (rising or falling depending on the value of the MCP bit
– rising refers to a rising edge on the XCLK signal, a falling edge on the XCLK* signal). Received data is formatted and
sent through an internal data bus P[23:0] to the LVDS data path. The input data formats are (IDF[2:0] = 0, 1, 2, 3 and 4):
IDF
0
1
2
3
4
The input data format is shown in Figure 4. The Pixel Data bus represents a 12-bit or 8-bit multiplexed data stream,
which contains either RGB or YCrCb formatted data. The input data rate is 2X the pixel rate, and each pair of Pn values
(e.g.; P0a and P0b) will contain a complete pixel encoded as shown in Table 2 through Table 4.
For multiplexed input data formats, data can be latched from the graphics controller by either rising only or falling only
clock edges, or by both rising and falling clock edges. The MCP bit selects the rising or the falling clock edge, where
rising refers to rising edge on the XCLK signals and falling edge on the XCLK*. It is assumed that the first clock cycle
following the leading edge of the incoming horizontal sync signal contains the first word (Pxa) of a pixel, if an active
pixel was present immediately following the horizontal sync. This does not mean that active data should immediately
follow the horizontal sync, however. When the input is a YCrCb data stream the color-difference data will be
transmitted at half the data rate of the luminance data, with the sequence being set as Cb, Y, Cr, Y, where Cb0,Y0,Cr0
refers to co-sited luminance and color-difference samples and the following Y1 byte refers to the next luminance sample,
per ITU-R BT.656 standards (the clock frequency is dependent upon the current mode, and is not 27MHz as specified in
ITU-R BT.656). All non-active pixels should be 0 in RGB formats, and 16 for Y, 128 for Cr and Cb in YCrCb formats.
201-0000-054
t
CD
CD
= - XCMD[3:0] * t
= (XCMD[3:0] – 8) * t
Data De-skew Feature
XCMD is a number between 0 and 15 represented as a binary code
t
Input Data Formats
Description
RGB 8-8-8 (2x12-bit)
RGB 8-8-8 (2x12-bit) or RGB 5-6-5 (2x8-bit)
RGB 5-6-5 (2x8bit)
RGB 5-5-5 (2x8-bit)
YCrCb 8-8 (2x8-bit)
STEP
is the adjustment increment (see Section 4.5)
H
XCLK
(2X)
XCLK
(1X)
DE
D[11:0]
Rev. 1.31, 6/14/2006
STEP
Figure 4: 12-bit Multiplexed Input Data Formats (IDF = 0,1,2,3, 4)
STEP
for 0 ≤ XCMD[3:0] ≤ 7
CD
between clock and data is given by the following formula:
for 8 ≤ XCMD[3:0] ≤ 15
(refer to Register 31h, bit 0)
P0a
P0b
P1a
P1b
P2a
P2b
CH7305
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