ch7305 Chrontel, ch7305 Datasheet - Page 12

no-image

ch7305

Manufacturer Part Number
ch7305
Description
Ch7305 Single/dual Channel Lvds Transmitter
Manufacturer
Chrontel
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ch7305A-TF
Manufacturer:
CHRONTEL
Quantity:
20 000
CHRONTEL
2.2.5
The LCD panel can be damaged if HSYNC is absent from the LVDS link. This situation can happen when there is a
catastrophic failure in the PC or the graphics system. The CH7305 is designed to prevent damage to the panel under such
a failure. If the system fails, the CH7305 does not expect any software instruction from the graphics controller to power
down the panel. Detection circuits are used to monitor the three timing signals – HSYNC, VSYNC and XCLK. If any
one, combination of, or all of these signals becomes unstable, the CH7305 will commence Power Down Sequencing
according to Section 2.2.4. A description of these detection circuits is shown in Figure 6.
The power up sequence can occur only if (a) XCLK is not missing, (b) there are no missing HSYNC and VSYNC, (c)
the PLL CLOCK is stable, and (d) PANEN is set to 1. The power down sequence happens if any of those conditions fails.
The power up sequence can also occur if the panel protection circuitry is bypassed.
The panel protection circuitry is comprised of a LOCKDET block, which detects an unstable clock from the LVDS PLL,
a SYNCDET block, which detects missing inputs HSYNC and VSYNC and an XCLK Detect block which detects
missing XCLK. XCLK stability (assuming it is not missing) is determined by the number of PLL unlock signals
generated within one frame. This number is programmable via serial port using the BGLMT register (Register 7Fh).
12
Panel Protection
XCLK
FOSC (from oscillator)
HSYNC
VSYNC
LSYNCEN
FIFO
Detect
XCLK
DETECT
LVDS
PLL
SYNC
Figure 6: Detection Circuits for Panel Protection
XCLK
LOCK
Reg. 14h [2]
Power Sequencing
CLKDETD
DETECT
LOCK
XCLK
Register 66h
LSYNCEN
LPFORC
SYNCST
LPLOCK
PANEN
LPLEN
BKLEN
LOCKST
LPFORC
LPLEN
Note:
1) LOCKST will be logic
low if either XCLK or the
LVDS PLL output is
unstable.
2) SYNCST will be logic
low if either Hsync or
Vsync is unstable or
missing.
201-0000-054
0
1
MUX
ENAVDD
ENABKL
Rev. 1.31,
CH7305
6/14/2006

Related parts for ch7305