ch7305 Chrontel, ch7305 Datasheet - Page 21

• Manufacturer Part Number: ch7305
• Description: Ch7305 Single/dual Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
SYNCST(bit 6) of the LPMC register is the Hsync and Vsync stability status bit. Refer to Section 2.2.5.
Power Sequencing T1
This register defines Power On time (T1), the time duration between LVDS_RDY (internal signal) to valid LVDS Clock
and Data. The entire bit field, TPON[8:0], is comprised of these bits TPON[7:0] plus TPON8 contained in the PST2
Power Sequencing T2 register (Register 68h, bit 7). Refer to Figure 5 and Table 7 in Section 2.2.4. The range of T1 is
2ms to 512ms in increments of 1ms.
201-0000-054
DEFAULT:
SYMBOL:
SYNCST
TYPE:
BIT:
= 0 => Hsync or Vsync are not stable
= 1 => Hsync and Vsync are stable
TPON7
R/W
Rev. 1.31, 6/14/2006
7
0
TPON6
R/W
6
0
TPON5
R/W
5
0
TPON4
R/W
4
0
TPON3
R/W
3
0
Symbol:
Address:
TPON2
R/W
2
0
TPON1
PST1
67h
R/W
1
0
CH7305
TPON0
R/W
0
0
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