ch7305 Chrontel, ch7305 Datasheet - Page 20

• Manufacturer Part Number: ch7305
• Description: Ch7305 Single/dual Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
LVDSDC (bit 4) of Register LVDSE1 allows single or dual channel LVDS to be selected. If the bit is 1, dual channel is
selected. If the bit is 0, single channel is selected.
LVDS24 (bit 5) of Register LVDSE1 selects LVDS 24 bit or 18 bit output format. A ‘1’ provides 24- bit output mode
and a ‘ 0’ provides 18- bit output mode.
LVDS Encoding 2 Register
LCNTLF and LCNTLE (bits 1-0) of Register LVDSE2 are OpenLDI miscellaneous control signals, Cntl F and Cntl E,
for the Display Source Serializer respectively. Refer to the OpenLDI specification v0.95. See Section 2.2.2.
LA3RL (bit 2), LA6RL (bit 3) and LA7RL (bit 4) of Register LVDSE2 are OpenLDI reserved bits for future use and
may take any value. Refer to the OpenLDI specification v0.95, P5. See Section 2.2.2.
LVDS PLL Miscellaneous Control Register
The LPMC register controls panel protection circuits which control the LVDS panel power up and down sequence.
Refer to Section 2.2.5 Panel Protection and to Figure 6 for more details.
PANEN (bit 0) of the LPMC register controls the LVDS panel enable.
LSYNCEN (bit 1) of the LPMC register controls the Sync Detection Bypass
LPLOCK (bit 2) of the LPMC register indicates the status of the PLL Lock
LPFORC (bit 3) of the LPMC register: Bypass LVDS Lock Detect Sentry
LPLEN (bit 4) of the LPMC register controls LVDS PLL Lock Enable between LPLOCK and LPFORC.
BKLEN (bit 5) of the LPMC register enables the panel backlight.
20
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
PANEN
LSYNCEN = 0 => Normal Operation. HSYNC and VSYNC detection enabled.
LPLOCK
Bit 3
LPLEN
BKLEN
TYPE:
TYPE:
BIT:
BIT:
Reserved
Reserved
= 0 => Begin Power off sequence
= 1 => Power-on
= 1 => HSYNC and VSYNC detection circuit is bypassed enabling forced power up sequence.
= 0 => PLL is not stable.
= 1 => PLL is stable and properly locked.
= 0 => Lock detect sentry is active.
= 1 => Lock detect sentry is overridden if LPLEN is set to ‘1’.
= 0 => Select LPLOCK (normal operation)
= 1 => Select LPFORC (Lock detect sentry is overridden if LPFORC is set to ‘1’)
= 0 => Disable Backlight
=1 => Enable Backlight
R/W
R/W
0
0
7
7
SYNCST
Reserved
R/W
R
6
0
6
0
Reserved
BKLEN
R/W
R/W
5
0
3
0
LA3RL
LPLEN LPFORC LPLOCK LSYNCEN PANEN
R/W
R/W
4
0
4
0
LA6RL
R/W
R/W
3
0
3
0
201-0000-054
Symbol:
Address:
Symbol:
Address:
LA7RL LCNTLE LCNTLF
R/W
R
2
0
2
0
Rev. 1.31,
R/W
LVDSE2
65h
LPMC
66h
R/W
1
0
1
0
CH7305
6/14/2006
R/W
R/W
0
0
0
1