ch7305 Chrontel, ch7305 Datasheet - Page 23

• Manufacturer Part Number: ch7305
• Description: Ch7305 Single/dual Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Power Sequencing T5
TPPWD[5:0] (bits 5-0) of Register PST5 define the Power Cycle time (T5), the waiting time required prior to enabling
power on after power has been off. Refer to Figure 5 and Table 7 in Section 2.2.4. The range is 2ms to 1600ms in
increments of 50ms.
LVDS PLL Feed Back Divider Control
LPFBD[3:0] (bits 3-0) of Register LPFBDC define the LVDS PLL Feed-Back Divider Control. The recommended
settings are shown in Table 16 in Section 3.4.
LPFFD[1:0] (bits 5:4) of Register LPFBDC define the LVDS PLL Feed-Forward Divider Control. The recommended
settings are shown in Table 16 in Section 3.4.
LVDS PLL VCO Control Register
LPVCO[3:0] (bits 3-0) of Register LPVC determine the LVDS PLL VCO open-loop frequency range. The
recommended settings are shown in Table 16 in Section 3.4.
LPPSD[1:0] (bits 5:4) of Register LPVC define the LVDS PLL post scale divider controls. The recommended settings
are shown in Table 16 in Section 3.4.
201-0000-054
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
Reserved Reserved
Reserved Reserved
Reserved Reserved
R/W
R/W
R/W
Rev. 1.31, 6/14/2006
1
1
7
7
7
1
R/W
R/W
R/W
6
1
6
0
6
0
TPPWD5 TPPWD4 TPPWD3 TPPWD2 TPPWD1 TPPWD0
LPFFD1 LPFFD0 LPFBD3 LPFBD2 LPFBD1
LPPSD1
R/W
R/W
R/W
5
0
5
1
5
0
LPPSD0 LPVCO3 LPVCO2 LPVCO1 LPVCO0
R/W
R/W
R/W
4
0
4
0
4
1
R/W
R/W
R/W
3
0
3
0
3
0
Symbol:
Address:
Symbol:
Address:
Symbol:
Address:
R/W
R/W
R/W
2
0
2
0
2
1
R/W
R/W
PST5
6Bh
LPFBDC
71h
LPVC
72h
R/W
1
0
1
1
1
1
CH7305
LPFBD0
R/W
R/W
R/W
0
1
0
1
0
0
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