ch7305 Chrontel, ch7305 Datasheet - Page 22

• Manufacturer Part Number: ch7305
• Description: Ch7305 Single/dual Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
Power Sequencing T2
TPBLE[6:0] (bits 6:0) of Register PST2 define the Back Light Enable time (T2), the waiting time after valid LVDS
Clock and Data before enabling the LVDS panel back light. Refer to Figure 5 and Table 7 in Section 2.2.4. The range
of T2 is 2ms to 256ms in increments of 2ms.
TPON8 (bit 7) of Register PST2 defines the MSB of the Power On time (T1). The entire bit field, TPON[8:0], is
comprised of this bit, TPON8, plus TPON[7:0] contained in the Power Sequencing T1 register (Register 67h). Refer to
the description of the PST1 register (Register 67h) for more information.
Power Sequencing T3
TPBLD[6:0] (bits 6-0) of Register PST3 define the Back Light Disable time (T3), the required time after disabling the
back light before the valid LVDS Clock and Data become tri-stated or disabled. Refer to Figure 5 and Table 7 in
Section 2.2.4. The range of T3 is 2ms to 256ms in increments of 2ms.
TPOFF8 (bit 7) of Register PST3 defines the MSB of the Power Off time (T4). The entire bit field, TPOFF[8:0], is
comprised of this bit, TPOFF8, plus TPOFF[7:0] contained in the Power Sequencing T4 register (Register 6Ah). Refer
to the description of the PST4 register (Register 6Ah) for more information.
Power Sequencing T4
Register PST4 defines the Power Off time (T4), the required time prior to power off after the valid LVDS Clock and
Data become tri-stated or disabled. The entire bit field, TPOFF[8:0], is comprised of these bits, TPOFF[7:0], plus
TPOFF8 contained in the Power Sequencing T3 register (Register 69h, bit 7). Refer to Figure 5 and Table 7 in
Section 2.2.4.
The range is 2ms to 512ms in increments of 1ms.
22
DEFAULT:
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
TPOFF7 TPOFF6
TP0FF8 TPBLD6 TPBLD5 TPBLD4 TPBLD3 TPBLD2 TPBLD1 TPBLD0
TPON8
R/W
R/W
R/W
0
0
7
0
7
7
TPBLE6 TPBLE5 TPBLE4 TPBLE3 TPBLE2 TPBLE1 TPBLE0
R/W
R/W
R/W
6
0
6
0
6
0
TPOFF5 TPOFF4 TPOFF3 TPOFF2 TPOFF1
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
R/W
R/W
R/W
3
0
3
0
3
0
201-0000-054
Symbol:
Address:
Symbol:
Address:
Symbol:
Address:
R/W
R/W
R/W
0
0
2
2
2
0
Rev. 1.31,
R/W
R/W
PST2
68h
PST3
69h
PST4
6Ah
R/W
1
0
1
0
1
0
CH7305
TPOFF0
6/14/2006
R/W
R/W
R/W
0
0
0
0
0
0