ch7305 Chrontel, ch7305 Datasheet - Page 26

• Manufacturer Part Number: ch7305
• Description: Ch7305 Single/dual Channel Lvds Transmitter
• Manufacturer: Chrontel

CHRONTEL
LPLF[2:0] (bits 6-4) of Register LPD control the LVDS PLL Loop Filter Resistor per the following table:
The recommended settings are shown in Table 16 in Section 3.4.
FRSTB (bit 7) of Register LPD controls the FIFO reset.
LVDS Control
LPPD[4:0] (bits 4-0) of Register LVCTL define the LVDS PLL Phase Detector Control. The recommended settings are
shown in Table 16 in Section 3.4.
LPLF[4:3] (bits 6-5) of Register LVCTL control the LVDS PLL Loop Filter Capacitor. The recommended settings are
shown in Table 16 in Section 3.4.
LPCP3 (bit 7) of Register LVCTL enables the LVDS PLL Static Phase Error Reduction. The default value is
recommended.
Bang Limit Control
This register limits the allowable occurrences of internal LVDS FIFO over and under-runs within one VGA frame.
The recommended setting is shown in Table 16 in Section 3.4.
26
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
FRSTB
LPCP3
TYPE:
TYPE:
BIT:
BIT:
BGLMT7 BGLMT6 BGLMT5 BGLMT4 BGLMT3 BGLMT2 BGLMT1 BGLMT0
LPLF2
Table 15: LVDS PLL Loop Filter Resistor
= 0 =>
= 1 =>
= 0 =>
= 1 =>
LPCP3
R/W
R/W
0
0
0
0
0
0
1
1
1
1
7
7
Enable FIFO Reset
Normal Operation
Static Phase Error Reduction Disabled
Static Phase Error Reduction Enabled
LPLF1
LPLF4
R/W
R/W
6
0
6
0
0
0
1
1
0
0
1
1
LPLF0
LPLF3
R/W
R/W
5
1
5
0
0
1
0
1
0
1
0
1
PLL Loop Filter Resistor Value (Ohm)
LPPD4
R/W
R/W
1
4
4
1
LPPD3
R/W
R/W
3
1
3
0
21,800
42,600
11,000
73,200
1800
2600
1000
3200
201-0000-054
Symbol:
Address:
Symbol:
Address:
LPPD2
R/W
R/W
2
0
2
0
LPPD1
Rev. 1.31,
R/W
R/W
LVCTL
78h
BGLMT
7Fh
1
0
1
0
CH7305
LPPD0
6/14/2006
R/W
R/W
0
0
0
0