W83194R-58 WINBOND [Winbond], W83194R-58 Datasheet

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W83194R-58

Manufacturer Part Number
W83194R-58
Description
100 MHZ AGP CLOCK FOR VIA CHIPSET
Manufacturer
WINBOND [Winbond]
Datasheet
1.0 GENERAL DESCRIPTION
The W83194R-37/-58 is a Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks
required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight
different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC
microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by
software setting (additional register0 bit2). AGP and PCI clocks are externally selectable with smooth
transitions. The W83194R-37/-58 provides AGP clocks especially for clone chipset, and makes
SDRAM in synchronous frequency with CPU or AGP clocks.
The W83194R-37/-58 provides I
each clock outputs and choose the 0.25%, 0.5% or 0.5%,1.5% center type spread spectrum to reduce
EMI.
The W83194R-37/-58 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply.
High drive PCI and SDRAM CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF
loads. CPU CLOCK outputs typically provide better than 1V /nS slew rate into 20 pF loads as
maintaining 50 5% duty cycle. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide
better than 0.5V /nS slew rate.
2.0 FEATURES
Supports Pentium , Pentium
4 CPU clocks
12 SDRAM clocks for 3 DIMs
Two AGP clocks
6 PCI synchronous clocks.
Optional single or mixed supply:
(V
Skew form CPU to PCI clock -1 to 4 nS, center 2.6 nS, AGP to CPU sync. skew 0 nS (250 pS)
SDRAM frequency synchronous to CPU or AGP clocks
Smooth frequency switch with selections from 60 to 100 MHz CPU (-37) and 66 to 150 MHz (-58)
I
Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal)
MODE pin for power Management
48 MHz for USB
24 MHz for super I/O
Packaged in 48-pin SSOP
2
0.5% or 1.5% (-37) and 0.25%, 0.5% (-58) center type spread spectrum to reduce EMI
C 2-Wire serial interface and I
DD
= V
DD
q3 = V
DD
q2 = V
100 MHZ AGP CLOCK FOR VIA CHIPSET
DD
q2b = 3.3V) or (V
2
C serial bus interface to program the registers to enable or disable
2
Pro, Pentium
C read back
- 1 -
DD
II, AMD and Cyrix CPUs with I
Preliminary W83194R-37/-58
= V
DD
q3 = V
DD
Publication Release Date: April 1999
q2 = 3.3V, V
2
DD
C.
q2b = 2.5V)
Revision A1

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W83194R-58 Summary of contents

Page 1

... The W83194R-37/- Clock Synthesizer for VIA chipset. W83194R-37 provides all clocks required for high-speed RISC or CISC microprocessor such as Intel PentiumPro, AMD or Cyrix. Eight different frequencies of CPU, W83194R-58 provides all clocks required for high-speed RISC or CISC microprocessor such as Intel PentiumII and also provides 16 different frequencies of CPU clocks by software setting (additional register0 bit2) ...

Page 2

... PIN CONFIGURATION * REF0/CPU3.3#_2.5 PCICLK_F/*FS1 PCICLK0/*FS2 PCICLK1 PCICLK2 PCICLK3 PCICLK4 CPU_STOP#/SDRAM11 PCI_STOP#/SDRAM10 SDRAM 9 SDRAM 8 4.0 BLOCK DIAGRAM X1 X2 *FS(0:2) 3 *MODE CPU3.3#_2.5 *SD_SEL# CPU_STOP# PCI_STOP# *SDATA *SCLK Preliminary W83194R-37/-58 1 VDD 2 3 Vss Xin 4 Xout 5 VDDq3 Vss VDDq3 15 ...

Page 3

... PCICLK_F/ *FS1 7 PCICLK 0/ *FS2 8 PCICLK [ 1:4 ] 10, 11, 12, 13 Preliminary W83194R-37/-58 I/O FUNCTION IN Crystal input with internal loading capacitors and feedback resistors. OUT Crystal output at 14.318 MHz nominally. I/O FUNCTION OUT Low skew (< 250 pS) clock outputs for host frequencies such as CPU, Chipset and Cache. V voltage for these outputs ...

Page 4

... DD V q2b 14, 19, 30, 36 Power supply for SDRAM, PCICLK and 48/24 MHz outputs. DD Vss 3, 9, 16, 22, 27, 33, 39, 45 Preliminary W83194R-37/-58 I/O 2 I/O Serial data 2-wire control interface 2 IN Serial clock 2-wire control interface I/O I/O Internal 250 K pull-up. Latched input for CPU3.3#_2.5 at initial power up. ...

Page 5

... FS1 FS0 CPU (MHz 100 6.2 W83194R-58 Frequency Selection Table FS2 FS1 FS0 CPU (MHz 112 66 124 133 83 95. 100 ...

Page 6

... MODE = 1, these functions are not available. A particular clock could be enabled as both the 2- wire serial control interface and one of these pins indicate that it should be enabled. The W83194R-37/-58 may be disabled in the low state according to the following table in order to reduce power consumption. All clocks are stopped in the low state, but maintain a valid high period on transitions from running to stop ...

Page 7

... Preliminary W83194R-37/-58 DESCRIPTION 0 = 1.5% Spread Spectrum Modulation (W83194R-37 0.5% Spread Spectrum Modulation 0 = 0.25% Center Type Spread Spectrum Modulation (W83194R-58 0.5% Center Type Spread Spectrum Modulation SSEL2 (Frequency table selection by software via I SSEL1 (Frequency table selection by software via I SSEL0 (Frequency table selection by software via Selection by hardware ...

Page 8

... W83194R-58 Frequency table selection by software via I Register0 Bit2 SSEL2 SSEL1 SSEL0 FUNCTION TABLE FUNCTION DESCRIPTION TRI-STATE NORMAL See table 8 ...

Page 9

... Register 4: Additional SDRAM Clock Register (1 = Active Inactive) BIT @POWERUP Preliminary W83194R-37/-58 PIN 40 CPUCLK3 (Active/Inactive) 41 CPUCLK2 (Active/Inactive) 43 CPUCLK1 (Active/Inactive) 44 CPUCLK0 (Active/Inactive) PIN - Reserved 7 PCICLK_F (Active/Inactive) 15 AGP0 (Active/Inactive) 14 PCICLK4 (Active/Inactive) 12 PCICLK3 (Active/Inactive) 11 PCICLK2 (Active/Inactive) ...

Page 10

... Register 6: Reserved Register BIT @POWERUP Preliminary W83194R-37/-58 PIN - Reserved - Reserved 17 SDRAM11 (Active/ Inactive) 18 SDRAM10 (Active/ Inactive) 20 SDRAM9 (Active/ Inactive) 21 SDRAM8 (Active/ Inactive) PIN - Reserved - Reserved - Reserved 47 AGP1 (Active/ Inactive) - Reserved ...

Page 11

... Skew (CPU-CPU), (PCI- PCI), (SDRAM-SDRAM) CPU/SDRAM Cycle to Cycle Jitter CPU/SDRAM Absolute Jitter Jitter Spectrum 20 dB Bandwidth from Center Output Rise (0.4V 2.0V) & Fall (2.0V 0.4V) Time Overshoot/Undershoot Beyond Power Rails Ring Back Exclusion Preliminary W83194R-37/-58 SYMBOL STG q2b = 2.375V~2. + SYM ...

Page 12

... Buffer Characteristics 9.4.1 Type 1 Buffer for CPU (0:3) PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.4V and 2.0V Rise/Fall Time Max. T Between 0.4V and 2.0V Preliminary W83194R-37/-58 q2b = 2.375V~2.9V + SYM. MIN. TYP. MAX ...

Page 13

... Between 0.8V and 2.0V 9.4.4 Type 4 Buffer for REF0 and SDRAM (0:11) PARAMETER Pull-up Current Min. Pull-up Current Max. Pull-down Current Min. Pull-down Current Max. Rise/Fall Time Min. Between 0.8V and 2.0V Rise/Fall Time Max. T Between 0.8V and 2.0V Preliminary W83194R-37/-58 SYMBOL MIN. TYP. I (min (max (min.) ...

Page 14

... CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU "clocks on latency" is less than 2 CPU clocks and clocks off latency is less then 2 CPU clocks. Preliminary W83194R-37/-58 SYM. MIN. ...

Page 15

... At the end of the power up timer (within 3 mS) outputs starts to toggle at the specified frequency. #2 REF0/CPU3.3#_2.5 #7 PCICLK_F/FS1 #8 PCICLK0/FS2 #25 24/MODE #26 48/FS0 All other clocks Preliminary W83194R-37/- reaches 2.5V, the logic level that is present on these DD 2.5V Output Output ...

Page 16

... These capacitor has typical values ranging from 4 pF. Device Pin V DD Device Pin Preliminary W83194R-37/-58 @3.3V) inside. The default state will be logic resistor should be place before the serious terminating resistor. Note V DD Series 10 K Terminating ...

Page 17

... Use of Ferrite Bead (FB) are recommended to further reduce the power supply noise. 5. The power supply race to the V resistance is negligible. FB1 VDD VDD Plane (3.3V) C1 C31 C32 C33 C34 Preliminary W83194R-37/-58 pin and the ground via. DD pins must be thick enough so that voltage drops across the trace DD VDD2 Plane ...

Page 18

... ORDERING INFORMATION PART NUMBER W83194R-37/-58 14.0 HOW TO READ THE TOP MARKING W83194R-37 28051234 814GBB W83194R-58 28051234 814GBB 1st line: Winbond logo and the type number: W83194R-37/-58 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 814 814: packages made in '98, week 14 G: assembly house ID ...

Page 19

... Winbond customers using or selling these products for use in such applications their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sale. Preliminary W83194R-37/-58 Winbond Electronics (H.K.) Ltd. Winbond Electronics North America Corp. ...

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