MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 12

no-image

MPC860DP

Manufacturer Part Number
MPC860DP
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC860DPCVR50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860DPCVR66D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860DPCZQ50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860DPCZQ66D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860DPVR50D4
Manufacturer:
FREESCAL
Quantity:
300
Part Number:
MPC860DPVR50D4
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
MPC860DPVR80D4
Manufacturer:
ROHM
Quantity:
64
Part Number:
MPC860DPZQ66D4
Manufacturer:
FREESCALE
Quantity:
20 000
Company:
Part Number:
MPC860DPZQ80D4
Quantity:
1
Bus Signal Timing
All output pins on the MPC860 have fast rise and fall times. Printed circuit (PC) trace interconnection length should
be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This
recommendation particularly applies to the address and data buses. Maximum PC trace lengths of 6 inches are
recommended. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the
PC traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher
capacitive loads because these loads create higher transient currents in the V
inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the
PLL supply pins.
9 Bus Signal Timing
Table 7
The maximum bus speed supported by the MPC860 is 66 MHz. Higher-speed parts must be operated in half-speed
bus mode (for example, an MPC860 used at 80 MHz must be configured for a 40 MHz bus).
The timing for the MPC860 bus shown assumes a 50-pF load for maximum delays and a 0-pF load for minimum
delays.
12
Num
B5
B1a
B1b
B1c
B1d
B1e
B1g
B1h
B1f
B1
B2
B3
B4
B7
provides the bus operation timing for the MPC860 at 33, 40, 50, and 66 MHz.
33
CLKOUT period
EXTCLK to CLKOUT phase skew
(EXTCLK > 15 MHz and MF <= 2)
EXTCLK to CLKOUT phase skew
(EXTCLK > 10 MHz and MF < 10)
CLKOUT phase jitter (EXTCLK >
15 MHz and MF <= 2)
CLKOUT phase jitter
CLKOUT frequency jitter (MF < 10)
CLKOUT frequency jitter (10 < MF
< 500)
CLKOUT frequency jitter (MF > 500)
1
Frequency jitter on EXTCLK
CLKOUT pulse width low
CLKOUT width high
CLKOUT rise time
CLKOUT fall time
CLKOUT to A(0:31), BADDR(28:30),
RD/WR, BURST, D(0:31), DP(0:3)
invalid
1
Characteristic
3
3
1
1
MPC860 Family Hardware Specifications, Rev. 7
2
Table 7. Bus Operation Timings
1
30.30
–0.90
–2.30
–0.60
–2.00
12.12
12.12
7.58
Min
33 MHz
30.30
Max
0.90
2.30
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
25.00
–0.90
–2.30
–0.60
–2.00
10.00
10.00
6.25
Min
40 MHz
30.30
Max
0.90
2.30
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
CC
20.00
–0.90
–2.30
–0.60
–2.00
8.00
8.00
5.00
Min
and GND circuits. Pull up all unused
50 MHz
30.30
Max
0.90
2.30
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
15.15
–0.90
–2.30
–0.60
–2.00
Freescale Semiconductor
6.06
6.06
3.80
Min
66 MHz
30.30
Max
0.90
2.30
0.60
2.00
0.50
2.00
3.00
0.50
4.00
4.00
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
%
%
%

Related parts for MPC860DP