MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 56

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MPC860DP

Manufacturer Part Number
MPC860DP
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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CPM Electrical Characteristics
11.7 SCC in NMSI Mode Electrical Specifications
Table 20
Table 21
Figure 55
56
1
2
1
2
Num
Num
100
101
102
103
104
105
106
107
108
100
102
103
104
105
106
107
108
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 2.25/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
The ratios SYNCCLK/RCLK1 and SYNCCLK/TCLK1 must be greater than or equal to 3/1.
Also applies to CD and CTS hold time when they are used as external sync signals.
provides the NMSI external clock timing.
provides the NMSI internal clock timing.
through
RCLK1 and TCLK1 width high
RCLK1 and TCLK1 width low
RCLK1 and TCLK1 rise/fall time
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge
CD1 setup Time to RCLK1 rising edge
RCLK1 and TCLK1 frequency
RCLK1 and TCLK1 rise/fall time
TXD1 active delay (from TCLK1 falling edge)
RTS1 active/inactive delay (from TCLK1 falling edge)
CTS1 setup time to TCLK1 rising edge
RXD1 setup time to RCLK1 rising edge
RXD1 hold time from RCLK1 rising edge
CD1 setup time to RCLK1 rising edge
Figure 57
show the NMSI timings.
Characteristic
MPC860 Family Hardware Specifications, Rev. 7
Characteristic
Table 20. NMSI External Clock Timing
Table 21. NMSI Internal Clock Timing
1
1
2
2
1/SYNCCLK + 5
1/SYNCCLK
0.00
0.00
5.00
5.00
5.00
5.00
Min
40.00
40.00
40.00
0.00
0.00
0.00
0.00
All Frequencies
Min
All Frequencies
SYNCCLK/3
Freescale Semiconductor
15.00
50.00
50.00
Max
30.00
30.00
Max
MHz
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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