MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 31

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MPC860DP

Manufacturer Part Number
MPC860DP
Description
Hardware Specifications
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Figure 18
Figure 19
Freescale Semiconductor
GPL_A[0:5],
GPL_A[0:5],
provides the timing for the asynchronous negated UPWAIT signal controlled by the UPM.
provides the timing for the synchronous external master access controlled by the GPCM.
GPL_B[0:5]
GPL_B[0:5]
BS_A[0:3],
BS_A[0:3],
Figure 17. Asynchronous UPWAIT Asserted Detection in UPM Handled Cycles Timing
Figure 18. Asynchronous UPWAIT Negated Detection in UPM Handled Cycles Timing
BS_B[0:3]
BS_B[0:3]
CLKOUT
CLKOUT
UPWAIT
UPWAIT
CSx
CSx
B37
B37
MPC860 Family Hardware Specifications, Rev. 7
B38
B38
Bus Signal Timing
31

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