MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 34

• Manufacturer Part Number: MPC860DP
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Bus Signal Timing
Table 9
Figure 24
34
1
These synchronous timings define when the WAITx signals are detected in order to freeze (or relieve) the
PCMCIA current cycle. The WAITx assertion will be effective only if it is detected 2 cycles before the PSL
timer expiration. See Chapter 16, “PCMCIA Interface,” in the MPC860 PowerQUICC User’s Manual.
Num
P44 A(0:31), REG valid to PCMCIA
P45 A(0:31), REG valid to ALE negation
P46 CLKOUT to REG valid
P47 CLKOUT to REG invalid
P48 CLKOUT to CE1, CE2 asserted
P49 CLKOUT to CE1, CE2 negated
P50 CLKOUT to PCOE, IORD, PCWE,
P51 CLKOUT to PCOE, IORD, PCWE,
P52 CLKOUT to ALE assert time
P53 CLKOUT to ALE negate time
P54 PCWE, IOWR negated to D(0:31)
P55 WAITA and WAITB valid to CLKOUT
P56 CLKOUT rising edge to WAITA and
PSHT = 0. Otherwise add PSHT times cycle time.
PSST = 1. Otherwise add PSST times cycle time.
shows the PCMCIA timing for the MPC860.
provides the PCMCIA access cycle timing for the external bus read.
Strobe asserted
IOWR assert time
IOWR negate time
invalid
rising edge
WAITB invalid
1
Characteristic
1
1
1
MPC860 Family Hardware Specifications, Rev. 7
1
Table 9. PCMCIA Timing
20.73
28.30
7.58
8.58
7.58
7.58
2.00
7.58
5.58
8.00
2.00
Min
—
—
33 MHz
15.58
15.58
15.58
11.00
11.00
15.58
15.58
Max
—
—
—
—
—
—
16.75
23.00
6.25
7.25
6.25
6.25
2.00
6.25
4.25
8.00
2.00
Min
40 MHz
14.25
14.25
14.25
14.25
14.25
11.00
11.00
Max
—
—
—
—
—
—
13.00
18.00
5.00
6.00
5.00
5.00
2.00
5.00
3.00
8.00
2.00
Min
—
—
50 MHz
13.00
13.00
13.00
13.00
13.00
11.00
11.00
Max
—
—
—
—
—
—
13.15
9.36
3.79
4.84
3.79
3.79
2.00
3.79
1.79
8.00
2.00
Min
Freescale Semiconductor
—
—
66 MHz
11.84
11.84
11.84
11.00
11.00
10.04
11.84
Max
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns