MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 19

• Manufacturer Part Number: MPC860DP
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

Freescale Semiconductor
1
2
3
4
5
6
7
B35a A(0:31), BADDR(28:30), and D(0:31)
B35b A(0:31), BADDR(28:30), and D(0:31)
Num
B35
B36
B37
B38
B39
B40
B41
B42
B43
values in one cycle) or the frequency of the jitter is fast (that is, it does not stay at an extreme value for a long time)
then the maximum allowed jitter on EXTAL can be up to 2%.
BG output is relevant when the MPC860 is selected to work with internal bus arbiter.
for BG input is relevant when the MPC860 is selected to work with external bus arbiter.
signal is asserted.
for read accesses controlled by chip-selects under control of the UPM in the memory controller, for data beats where
DLT3 = 1 in the UPM RAM words. (This is only the case where data is latched on the falling edge of CLKOUT.)
Phase and frequency jitter performance results are only valid if the input jitter is less than the prescribed value.
If the rate of change of the frequency of EXTAL is slow (that is, it does not jump between the minimum and maximum
The timings specified in B4 and B5 are based on full strength clock.
The timing for BR output is relevant when the MPC860 is selected to work with external bus arbiter. The timing for
The timing required for BR input is relevant when the MPC860 is selected to work with internal bus arbiter. The timing
The D(0:31) and DP(0:3) input timings B18 and B19 refer to the rising edge of the CLKOUT in which the TA input
The D(0:31) and DP(0:3) input timings B20 and B21 refer to the falling edge of the CLKOUT. This timing is valid only
A(0:31), BADDR(28:30) to CS
valid—as requested by control bit
BST4 in the corresponding word in
UPM
to BS valid—as requested by control
bit BST1 in the corresponding word
in UPM
to BS valid—as requested by control
bit BST2 in the corresponding word
in UPM
A(0:31), BADDR(28:30), and D(0:31)
to GPL valid—as requested by
control bit GxT4 in the corresponding
word in UPM
UPWAIT valid to CLKOUT falling
edge
CLKOUT falling edge to UPWAIT
valid
AS valid to CLKOUT rising edge
A(0:31), TSIZ(0:1), RD/WR, BURST,
valid to CLKOUT rising edge
TS valid to CLKOUT rising edge
(setup time)
CLKOUT rising edge to TS valid
(hold time)
AS negation to memory controller
signals negation
9
9
Characteristic
Table 7. Bus Operation Timings (continued)
MPC860 Family Hardware Specifications, Rev. 7
10
13.15
20.73
5.58
5.58
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
33 MHz
Max
TBD
—
—
—
—
—
—
—
—
—
—
10.50
16.75
4.25
4.25
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
40 MHz
Max
TBD
—
—
—
—
—
—
—
—
—
—
13.00
3.00
8.00
3.00
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
50 MHz
TBD
Max
—
—
—
—
—
—
—
—
—
—
1.79
5.58
9.36
1.79
6.00
1.00
7.00
7.00
7.00
2.00
Min
—
66 MHz
Bus Signal Timing
Max
TBD
—
—
—
—
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
19