MPC860DP FREESCALE [Freescale Semiconductor, Inc], MPC860DP Datasheet - Page 66

• Manufacturer Part Number: MPC860DP
• Description: Hardware Specifications
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

CPM Electrical Characteristics
Table 27
Figure 68
66
1
1
Num
Num
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
The ratio SYNCCLK/(BRGCLK / pre_scaler) must be greater than or equal to 4/1.
210
211
200
200
202
203
204
205
206
207
208
209
210
211
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3 × pre_scaler × 2).
SCL frequency is given by SCL = BRGCLK_frequency / ((BRG register + 3) × pre_scaler × 2).
SDA
SCL
provides the I
shows the I
SDL/SCL fall time
Stop condition setup time
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
High period of SCL
Start condition setup time
Start condition hold time
Data hold time
Data setup time
SDL/SCL rise time
SDL/SCL fall time
Stop condition setup time
205
202
2
C bus timing.
2
C (SCL > 100 kHz) timings.
206
Characteristic
Table 26. I
203
MPC860 Family Hardware Specifications, Rev. 7
Table 27. . I
Characteristic
Figure 68. I
1
2
C Timing (SCL < 100 kH
207
2
C Timing (SCL > 100 kH
2
209
C Bus Timing Diagram
Expression
fSCL
fSCL
204
210
BRGCLK/16512
Z
1/2(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(2.2 * fSCL)
1/(40 * fSCL)
) (continued)
Min
—
—
0
0
Z
)
All Frequencies
Min
4.7
All Frequencies
—
208
1/(10 * fSCL)
1/(33 * fSCL)
BRGCLK/48
BRGCLK/48
Max
Freescale Semiconductor
211
—
—
—
—
—
—
—
—
Max
300
—
Unit
Unit
Hz
Hz
ns
µs
s
s
s
s
s
s
s
s
s
s