LAN9217-MT-E2 SMSC [SMSC Corporation], LAN9217-MT-E2 Datasheet - Page 31

• Manufacturer Part Number: LAN9217-MT-E2
• Description: 16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
• Manufacturer: SMSC [SMSC Corporation]

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX
Datasheet
SMSC LAN9217
3.10.2.1
Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9217
will timeout, and the EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3.2, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an
EEPROM Read or Write operation.
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.
Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in
page 95
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.
the EEPROM the host must first issue the EWEN command.
for E2P_CMD field settings for each command.
Busy Bit = 0
EEPROM Write
Figure 3.2 EEPROM Access Flow Diagram
Write Data
Command
Command
Register
Register
Register
Write
Read
Idle
DATASHEET
Section 5.3.23, "E2P_CMD – EEPROM Command Register," on
31
EEPROM Read
Read Data
Command
Command
Register
Register
Register
Write
Read
Idle
Busy Bit = 0
Revision 1.5 (07-18-06)